Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6654271 | Method for reading and storing binary memory cells signals and circuit arrangement | Athanasia Chrysostomides, Dominique Savignac | 2003-11-25 |
| 6560134 | Memory configuration with a central connection area | Martin Brox, Helmut Schneider, Robert Kaiser, Dominique Savignac | 2003-05-06 |
| 6310793 | Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines | Martin Brox | 2001-10-30 |
| 6295236 | Semiconductor memory of the random access type with a bus system organized in two planes | Martin Brox | 2001-09-25 |
| 6226219 | Semiconductor memory with a plurality of memory banks | Thoai-Thai Le, Andrea Trunk | 2001-05-01 |
| 6138214 | Synchronous dynamic random access memory architecture for sequential burst mode | — | 2000-10-24 |
| 6078534 | Semiconductor memory having redundancy circuit | Martin Gall | 2000-06-20 |
| 5978931 | Variable domain redundancy replacement configuration for a memory device | Toshiaki Kirihata, Garbiel Daniel, Jean-Marc Dortu | 1999-11-02 |
| 5970000 | Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains | Toshiaki Kirihata | 1999-10-19 |
| 5881003 | Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration | Toshiaki Kirihata, Garbiel Daniel, Jean-Marc Dortu | 1999-03-09 |