Issued Patents All Time
Showing 26–50 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10693005 | Reliable gate contacts over active areas | Emre Alptekin, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran | 2020-06-23 |
| 10614877 | 4T static random access memory bitcell retention | Myung-Hee Na, Robert C. Wong, Sean D. Burns, Jens Haetty | 2020-04-07 |
| 10529625 | 3D vertical FET with top and bottom gate contacts | Brent A. Anderson | 2020-01-07 |
| 10424574 | Standard cell architecture with at least one gate contact over an active area | Myung-Hee Na, Ravikumar Ramachandran | 2019-09-24 |
| 10424576 | Standard cell architecture with at least one gate contact over an active area | Myung-Hee Na, Ravikumar Ramachandran | 2019-09-24 |
| 10381338 | Metal fill optimization for self-aligned double patterning | Lawrence A. Clevenger, Ximeng Guan, Myung-Hee Na | 2019-08-13 |
| 10381480 | Reliable gate contacts over active areas | Emre Alptekin, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran | 2019-08-13 |
| 10361128 | 3D vertical FET with top and bottom gate contacts | Brent A. Anderson | 2019-07-23 |
| 10074570 | 3D vertical FET with top and bottom gate contacts | Brent A. Anderson | 2018-09-11 |
| 9954529 | Ultra dense vertical transport FET circuits | Brent A. Anderson, Edward J. Nowak | 2018-04-24 |
| 9859898 | High density vertical field effect transistor multiplexer | Brent A. Anderson | 2018-01-02 |
| 9761712 | Vertical transistors with merged active area regions | Brent A. Anderson, Terence B. Hook, Seong-Dong Kim | 2017-09-12 |
| 9735029 | Metal fill optimization for self-aligned double patterning | Lawrence A. Clevenger, Ximeng Guan, Myung-Hee Na | 2017-08-15 |
| 9680473 | Ultra dense vertical transport FET circuits | Brent A. Anderson, Edward J. Nowak | 2017-06-13 |
| 9460811 | Read only memory (ROM) with redundancy | George M. Braceras, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer +2 more | 2016-10-04 |
| 9424386 | Generating place and route abstracts | Lars Liebmann | 2016-08-23 |
| 9202554 | Methods and circuits for generating physically unclonable function | Nazmul Habib, Daryl M. Seitzer, Rohit Shetty | 2015-12-01 |
| 9052356 | Embedded photon emission calibration (EPEC) | Ronald A. Piro, Daryl M. Seitzer, Rohit Shetty, Thomas W. Wyckoff | 2015-06-09 |
| 8934312 | Process variation skew in an SRAM column architecture | Daryl M. Seitzer, Rohit Shetty | 2015-01-13 |
| 8862417 | Systems and methods for determining adjustable wafer acceptance criteria based on chip characteristics | Eric Johnson, William J. Rensch, Manikandan Viswanath | 2014-10-14 |
| 8856715 | Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP) | Jason E. Stephens, Vikrant Chauhan, Lawrence A. Clevenger, Ning Lu | 2014-10-07 |
| 8839054 | Read only memory (ROM) with redundancy | George M. Braceras, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer +2 more | 2014-09-16 |
| 8726210 | Optimizing timing critical paths by modulating systemic process variation | Manikandan Viswanath | 2014-05-13 |
| 8643987 | Current leakage in RC ESD clamps | Joseph A. Iadanza, Mujahid Muhammad, Daryl M. Seitzer, Rohit Shetty, Jane S. Tu | 2014-02-04 |
| 8576526 | Reduced current leakage in RC ESD clamps | Mujahid Muhammad, Daryl M. Seitzer, Rohit Shetty | 2013-11-05 |