Issued Patents All Time
Showing 26–50 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11646358 | Sacrificial fin for contact self-alignment | Yann Mignot, Indira Seshadri, Su Chen Fan, Christopher J. Waskiewicz | 2023-05-09 |
| 11646235 | Vertical tunneling field effect transistor with dual liner bottom spacer | Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John R. Sporre | 2023-05-09 |
| 11615992 | Substrate isolated VTFET devices | Marc A. Bergendahl, Kangguo Cheng, John R. Sporre, Gauri Karve, Fee Li Lie | 2023-03-28 |
| 11605717 | Wrapped-around contact for vertical field effect transistor top source-drain | Ruilong Xie, Jeffrey C. Shearer, Su Chen Fan, Heng Wu | 2023-03-14 |
| 11557589 | Air gap spacer for metal gates | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2023-01-17 |
| 11462631 | Sublithography gate cut physical unclonable function | Kangguo Cheng, Fee Li Lie, Gauri Karve, Marc A. Bergendahl, John R. Sporre | 2022-10-04 |
| 11430753 | Iterative formation of damascene interconnects | Sean P. Kilcoyne, Michael V. Liguori, Michael J. Rondon | 2022-08-30 |
| 11424367 | Wrap-around contacts including localized metal silicide | Julien Frougier, Yann Mignot, Andrew M. Greene | 2022-08-23 |
| 11393869 | Wafer level shim processing | Jeffery H. Burkhart, Sean P. Kilcoyne | 2022-07-19 |
| 11316029 | Sacrificial fin for contact self-alignment | Yann Mignot, Indira Seshadri, Su Chen Fan, Christopher J. Waskiewicz | 2022-04-26 |
| 11257681 | Using a same mask for direct print and self-aligned double patterning of nanosheets | Stuart A. Sieg, Daniel James Dechene | 2022-02-22 |
| 11251287 | Self-aligned uniform bottom spacers for VTFETS | Ruilong Xie, Hemanth Jagannathan, Jay William Strane | 2022-02-15 |
| 11245027 | Bottom source/drain etch with fin-cut-last-VTFET | Tao Li, Indira Seshadri, Nelson Felix | 2022-02-08 |
| 11239316 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Robert R. Robison, John R. Sporre +1 more | 2022-02-01 |
| 11222813 | Method of manufacturing wafer level low melting temperature interconnections | Sean P. Kilcoyne, George Grama | 2022-01-11 |
| 11189532 | Dual width finned semiconductor structure | Yi Song, Jay William Strane, Fee Li Lie, Richard A. Conti | 2021-11-30 |
| 11152266 | Vertical tunneling field effect transistor with dual liner bottom spacer | Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John R. Sporre | 2021-10-19 |
| 11127815 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Gauri Karve, Fee Li Lie, Robert R. Robison, John R. Sporre +1 more | 2021-09-21 |
| 11075299 | Transistor gate having tapered segments positioned above the fin channel | Gauri Karve, Marc A. Bergendahl, Fee Li Lie, Kangguo Cheng, Sean Teehan | 2021-07-27 |
| 11043581 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, John R. Sporre, Sean Teehan | 2021-06-22 |
| 10985025 | Fin cut profile using fin base liner | Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz | 2021-04-20 |
| 10937892 | Nano multilayer carbon-rich low-k spacer | Donald F. Canaperi, Richard A. Conti, Thomas J. Haigh, Jr., Son V. Nguyen | 2021-03-02 |
| 10937810 | Sub-fin removal for SOI like isolation with uniform active fin height | Marc A. Bergendahl, Kangguo Cheng, Gauri Karve, Fee Li Lie, John R. Sporre +1 more | 2021-03-02 |
| 10886271 | Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition | Kangguo Cheng, Fee Li Lie, Sean Teehan | 2021-01-05 |
| 10847569 | Wafer level shim processing | Jeffery H. Burkhart, Sean P. Kilcoyne | 2020-11-24 |