Issued Patents All Time
Showing 51–75 of 542 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11430735 | Barrier removal for conductor in top via integration scheme | Nicholas Anthony Lanzillo, Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi, Robert R. Robison | 2022-08-30 |
| 11302575 | Subtractive line with damascene second line type | Christopher J. Penny, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison | 2022-04-12 |
| 11295978 | Interconnects having spacers for improved top via critical dimension and overlay tolerance | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2022-04-05 |
| 11289371 | Top vias with selectively retained etch stops | Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison | 2022-03-29 |
| 11282768 | Fully-aligned top-via structures with top-via trim | Kenneth Chun Kuen Cheng, Koichi Motoyama, Joseph F. Maniscalco | 2022-03-22 |
| 11276639 | Conductive lines with subtractive cuts | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison | 2022-03-15 |
| 11276611 | Top via on subtractively etched conductive line | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison | 2022-03-15 |
| 11270913 | BEOL metallization formation | Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama, Somnath Ghosh | 2022-03-08 |
| 11271106 | Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2022-03-08 |
| 11257721 | Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2022-02-22 |
| 11239360 | Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy | Shogo Mochizuki, Hemanth Jagannathan, Junli Wang | 2022-02-01 |
| 11232977 | Stepped top via for via resistance reduction | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2022-01-25 |
| 11205723 | Selective source/drain recess for improved performance, isolation, and scaling | Ardasheir Rahman, Junli Wang, Stuart A. Sieg, Christopher J. Waskiewicz | 2021-12-21 |
| 11195795 | Well-controlled edge-to-edge spacing between adjacent interconnects | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2021-12-07 |
| 11195792 | Top via stack | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2021-12-07 |
| 11189568 | Top via interconnect having a line with a reduced bottom dimension | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2021-11-30 |
| 11177132 | Self aligned block masks for implantation control | Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang | 2021-11-16 |
| 11177166 | Etch stop layer removal for capacitance reduction in damascene top via integration | Christopher J. Penny, Lawrence A. Clevenger, Robert R. Robison, Kisik Choi, Nicholas Anthony Lanzillo | 2021-11-16 |
| 11171084 | Top via with next level line selective growth | Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison | 2021-11-09 |
| 11164777 | Top via with damascene line and via | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison | 2021-11-02 |
| 11158537 | Top vias with subtractive line formation | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2021-10-26 |
| 11152507 | Vertical field-effect transistor with a bottom contact that exhibits low electrical resistance | Chen Zhang, Tenko Yamashita, Terence B. Hook | 2021-10-19 |
| 11145550 | Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor | Junli Wang, Albert M. Young | 2021-10-12 |
| RE48616 | Isolation region fabrication for replacement gate processing | Edward J. Nowak | 2021-06-29 |
| 11031296 | 3D vertical FET with top and bottom gate contacts | Albert M. Chu | 2021-06-08 |