Issued Patents All Time
Showing 76–100 of 542 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11024546 | Vertical field effect transistors | Edward J. Nowak | 2021-06-01 |
| 11011513 | Integrating a junction field effect transistor into a vertical field effect transistor | Huiming Bu, Terence B. Hook, Xuefeng Liu, Junli Wang | 2021-05-18 |
| 10991619 | Top via process accounting for misalignment by increasing reliability | Chen Zhang, Lawrence A. Clevenger, Benjamin D. Briggs, Chih-Chao Yang | 2021-04-27 |
| 10985257 | Vertical transport fin field effect transistor with asymmetric channel profile | Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2021-04-20 |
| 10985073 | Vertical field effect transistor replacement metal gate fabrication | Ruilong Xie, Wenyu Xu, Zuoguang Liu | 2021-04-20 |
| 10978454 | Semiconductor device and method of forming the semiconductor device | Shawn P. Fetterolf, Terence B. Hook | 2021-04-13 |
| 10964812 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Terence B. Hook, Gauri Karve | 2021-03-30 |
| 10957794 | Vertical transistor contact for cross-coupling in a memory cell | Terence B. Hook, Junli Wang | 2021-03-23 |
| 10957696 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Ruqiang Bao, Dechao Guo, Vijay Narayanan | 2021-03-23 |
| 10943831 | Vertical field effect transistors | Edward J. Nowak | 2021-03-09 |
| 10943911 | Vertical transport devices with greater density through modified well shapes | Stuart A. Sieg, Junli Wang | 2021-03-09 |
| 10943992 | Transistor having straight bottom spacers | Kangguo Cheng, Christopher J. Waskiewicz, Michael P. Belyansky, Muthumanickam Sankarapandian, Puneet Harischandra Suvarna +1 more | 2021-03-09 |
| 10937793 | Vertical transistor contact for a memory cell with increased density | Terence B. Hook, Junli Wang | 2021-03-02 |
| 10903361 | Fabrication of a vertical field effect transistor device with a modified vertical fin geometry | Edward J. Nowak | 2021-01-26 |
| 10896972 | Self-aligned contact for vertical field effect transistor | Steven R. Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie | 2021-01-19 |
| 10896857 | Vertical field effect transistors | Edward J. Nowak | 2021-01-19 |
| 10879112 | Self-aligned via forming to conductive line and related wiring structure | Edward J. Nowak | 2020-12-29 |
| 10840373 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Terence B. Hook, Gauri Karve | 2020-11-17 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Ruqiang Bao, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10811528 | Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs | Mona A. Ebrish, Xuefeng Liu, Huiming Bu, Junli Wang | 2020-10-20 |
| 10811507 | Vertical transistors having multiple gate thicknesses for optimizing performance and device density | Fee Li Lie, Stuart A. Sieg, Junli Wang | 2020-10-20 |
| 10811508 | Vertical transistors having multiple gate thicknesses for optimizing performance and device density | Fee Li Lie, Stuart A. Sieg, Junli Wang | 2020-10-20 |
| 10777659 | Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors | Choonghyun Lee, Ruqiang Bao, Shogo Mochizuki, Hemanth Jagannathan | 2020-09-15 |
| 10777469 | Self-aligned top spacers for vertical FETs with in situ solid state doping | Ruqiang Bao, Junli Wang, Xin Miao | 2020-09-15 |
| 10755017 | Cell placement in a circuit with shared inputs and outputs | Laura R. Darden, Albert M. Chu, Alexander J. Suess | 2020-08-25 |