Issued Patents All Time
Showing 26–50 of 542 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12040250 | Heat pipe for vertically stacked field effect transistors | Terence B. Hook, Anthony I. Chou | 2024-07-16 |
| 12034005 | Self-aligned metal gate with poly silicide for vertical transport field-effect transistors | Ruqiang Bao, Dechao Guo, Vijay Narayanan | 2024-07-09 |
| 12001772 | Ultra-short-height standard cell architecture | Albert M. Chu, Junli Wang | 2024-06-04 |
| 12002874 | Buried power rail contact | Junli Wang, Ruilong Xie, Chen Zhang, Heng Wu | 2024-06-04 |
| 11990410 | Top via interconnect having a line with a reduced bottom dimension | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-05-21 |
| 11961759 | Interconnects having spacers for improved top via critical dimension and overlay tolerance | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-04-16 |
| 11915966 | Backside power rail integration | Ruilong Xie, Takeshi Nogami, Roy R. Yu, Balasubramanian Pranatharthiharan, Albert M. Young +1 more | 2024-02-27 |
| 11901440 | Sacrificial fin for self-aligned contact rail formation | Yann Mignot, Christopher J. Waskiewicz, Su Chen Fan, Junli Wang | 2024-02-13 |
| 11894265 | Top via with damascene line and via | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison | 2024-02-06 |
| 11869808 | Top via process with damascene metal | Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison | 2024-01-09 |
| 11855191 | Vertical FET with contact to gate above active fin | Junli Wang, Indira Seshadri, Chen Zhang, Ruilong Xie, Joshua M. Rubin +1 more | 2023-12-26 |
| 11842961 | Advanced metal interconnects with a replacement metal | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo | 2023-12-12 |
| 11830774 | Buried contact through fin-to-fin space for vertical transport field effect transistor | Junli Wang | 2023-11-28 |
| 11823998 | Top via with next level line selective growth | Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison | 2023-11-21 |
| 11804406 | Top via cut fill process for line extension reduction | Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2023-10-31 |
| 11791258 | Conductive lines with subtractive cuts | Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison | 2023-10-17 |
| 11764298 | VTFET with buried power rails | Chen Zhang, Ruilong Xie, Heng Wu, Junli Wang | 2023-09-19 |
| 11710666 | Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor | Junli Wang, Albert M. Young | 2023-07-25 |
| 11688775 | Method of forming first and second contacts self-aligned top source/drain region of a vertical field-effect transistor | Juntao Li, Kangguo Cheng | 2023-06-27 |
| 11670542 | Stepped top via for via resistance reduction | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2023-06-06 |
| 11658116 | Interconnects on multiple sides of a semiconductor structure | Junli Wang, Albert M. Chu, Dechao Guo | 2023-05-23 |
| 11600565 | Top via stack | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2023-03-07 |
| 11563003 | Fin top hard mask formation after wafer flipping process | Chen Zhang, Tenko Yamashita, Joshua M. Rubin | 2023-01-24 |
| 11538939 | Controlled bottom junctions | Ruilong Xie, Juntao Li, Kangguo Cheng | 2022-12-27 |
| 11437317 | Single-mask alternating line deposition | Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison | 2022-09-06 |