CP

Christopher J. Penny

IBM: 150 patents #285 of 70,183Top 1%
TE Tessera: 11 patents #38 of 271Top 15%
AS Adeia Semiconductor Solutions: 2 patents #9 of 57Top 20%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
📍 Saratoga Springs, NY: #3 of 363 inventorsTop 1%
🗺 New York: #212 of 115,490 inventorsTop 1%
Overall (All Time): #5,065 of 4,157,543Top 1%
165
Patents All Time

Issued Patents All Time

Showing 26–50 of 165 patents

Patent #TitleCo-InventorsDate
11430735 Barrier removal for conductor in top via integration scheme Brent A. Anderson, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Kisik Choi, Robert R. Robison 2022-08-30
11373880 Creating different width lines and spaces in a metal layer Ekmini Anuja De Silva, Ashim Dutta, Abraham Arceo de la Pena 2022-06-28
11351811 Optically-passive magnetic signature and identification feature with electromagnetic tamper detection Michael Rizzolo, Marc A. Bergendahl, Christopher J. Waskiewicz 2022-06-07
11348872 Hybrid dielectric scheme for varying liner thickness and manganese concentration Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Takeshi Nogami, Michael Rizzolo 2022-05-31
11348060 Increasing cost benefit and energy efficiency with modular delivery drones in inclement weather Benjamin D. Briggs, Leigh Anne H. Clevenger, Aldis Sipolins, Michael Rizzolo, Lawrence A. Clevenger 2022-05-31
11315827 Skip via connection between metallization levels Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha, Nicholas Anthony Lanzillo 2022-04-26
11302575 Subtractive line with damascene second line type Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2022-04-12
11302205 Language learning and speech enhancement through natural language processing Mahmoud Amin, Zhenxing Bi, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Krishna R. Tunga +1 more 2022-04-12
11295978 Interconnects having spacers for improved top via critical dimension and overlay tolerance Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2022-04-05
11289371 Top vias with selectively retained etch stops Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2022-03-29
11276639 Conductive lines with subtractive cuts Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2022-03-15
11276611 Top via on subtractively etched conductive line Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2022-03-15
11263068 Proximity correction in three-dimensional manufacturing Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Aldis Sipolins 2022-03-01
11263059 Load leveler Jonathan Fry, Marc A. Bergendahl, Christopher J. Waskiewicz, Jean Wynne, James J. Demarest 2022-03-01
11244859 Interconnects having a via-to-line spacer for preventing short circuit events between a conductive via and an adjacent line Koichi Motoyama, Cornelius Brown Peethala, Nicholas Anthony Lanzillo, Lawrence A. Clevenger 2022-02-08
11232977 Stepped top via for via resistance reduction Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2022-01-25
11227793 Self-aligned pattern formation for a semiconductor device Sean D. Burns, Lawrence A. Clevenger, Nelson Felix, Sivananda K. Kanakasabapathy, Nicole Saulnier 2022-01-18
11217481 Fully aligned top vias Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Robert R. Robison, Lawrence A. Clevenger 2022-01-04
11210968 Behavior-based interactive educational sessions Lawrence A. Clevenger, Stefania Axo, Leigh Anne H. Clevenger, Krishna R. Tunga, Mahmoud Amin +4 more 2021-12-28
11195792 Top via stack Brent A. Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison 2021-12-07
11195795 Well-controlled edge-to-edge spacing between adjacent interconnects Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2021-12-07
11189568 Top via interconnect having a line with a reduced bottom dimension Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2021-11-30
11177166 Etch stop layer removal for capacitance reduction in damascene top via integration Brent A. Anderson, Lawrence A. Clevenger, Robert R. Robison, Kisik Choi, Nicholas Anthony Lanzillo 2021-11-16
11177162 Trapezoidal interconnect at tight BEOL pitch Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Junli Wang, Koichi Motoyama +1 more 2021-11-16
11171084 Top via with next level line selective growth Brent A. Anderson, Lawrence A. Clevenger, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison 2021-11-09