| 12142525 |
Self-aligning spacer tight pitch via |
Brent A. Anderson, Nicholas Anthony Lanzillo |
2024-11-12 |
| 12106963 |
Self aligned pattern formation post spacer etchback in tight pitch configurations |
Sean D. Burns, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy, Christopher J. Penny +2 more |
2024-10-01 |
| 12087691 |
Semiconductor structures with backside gate contacts |
Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Nicolas Loubet, Dechao Guo +3 more |
2024-09-10 |
| 11990410 |
Top via interconnect having a line with a reduced bottom dimension |
Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2024-05-21 |
| 11980110 |
Insulated phase change memory using porous dielectrics |
Timothy Mathew Philip, Anirban Chandra, Kevin W. Brew |
2024-05-07 |
| 11977614 |
Circuit design watermarking |
Carl Radens, Daniel James Dechene, Hsueh-Chung Chen |
2024-05-07 |
| 11961759 |
Interconnects having spacers for improved top via critical dimension and overlay tolerance |
Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2024-04-16 |
| 11955424 |
Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device |
Benjamin D. Briggs, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo |
2024-04-09 |
| 11901224 |
Rework for metal interconnects using etch and thermal anneal |
Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang |
2024-02-13 |
| 11894265 |
Top via with damascene line and via |
Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison |
2024-02-06 |
| 11875987 |
Contacts having a geometry to reduce resistance |
Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang |
2024-01-16 |
| 11869808 |
Top via process with damascene metal |
Brent A. Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert R. Robison |
2024-01-09 |
| 11869783 |
Optimizating semiconductor binning by feed-forward process adjustment |
Benjamin D. Briggs, Nicholas Anthony Lanzillo, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis |
2024-01-09 |
| 11854884 |
Fully aligned top vias |
Nicholas Anthony Lanzillo, Koichi Motoyama, Somnath Ghosh, Christopher J. Penny, Robert R. Robison |
2023-12-26 |
| 11842961 |
Advanced metal interconnects with a replacement metal |
Kisik Choi, Nicholas Anthony Lanzillo, Brent A. Anderson |
2023-12-12 |
| 11830778 |
Back-side wafer modification |
David Wolpert, Daniel James Dechene, Michael Romain, Somnath Ghosh |
2023-11-28 |
| 11823998 |
Top via with next level line selective growth |
Brent A. Anderson, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert R. Robison |
2023-11-21 |
| 11812676 |
Multi-terminal phase change memory device |
Timothy Mathew Philip, Kevin W. Brew |
2023-11-07 |
| 11804406 |
Top via cut fill process for line extension reduction |
Christopher J. Penny, Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Robert R. Robison |
2023-10-31 |
| 11800817 |
Phase change memory cell galvanic corrosion prevention |
Injo Ok, Nicole Saulnier, Kevin W. Brew, Steven Michael McDermott, Hari Prasad Amanapu +2 more |
2023-10-24 |
| 11800819 |
Integrated diode memory device |
Timothy Mathew Philip, Kevin W. Brew |
2023-10-24 |
| 11790072 |
Paint on micro chip touch screens |
Maryam Ashoori, Benjamin D. Briggs, Justin A. Canaperi, Leigh Anne H. Clevenger, Michael Rizzolo +1 more |
2023-10-17 |
| 11791258 |
Conductive lines with subtractive cuts |
Brent A. Anderson, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert R. Robison |
2023-10-17 |
| 11779918 |
3D nanochannel interleaved devices |
Kangguo Cheng, Donald F. Canaperi, Shawn P. Fetterolf |
2023-10-10 |
| 11756887 |
Backside floating metal for increased capacitance |
Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang |
2023-09-12 |
