Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424550 | Buried metal signal rail for memory arrays | Biswanath Senapati, Seiji Munetoh, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Kohji Hosokawa | 2025-09-23 |
| 12255656 | Split pulse width modulation to reduce crossbar array integration time | Masatoshi Ishii, Pritish Narayanan | 2025-03-18 |
| 12148682 | Memory cell in wafer backside | Biswanath Senapati, Seiji Munetoh, Nicholas Anthony Lanzillo, Lawrence A. Clevenger, Kohji Hosokawa | 2024-11-19 |
| 12111878 | Efficient processing of convolutional neural network layers using analog-memory-based hardware | Benjamin Killeen | 2024-10-08 |
| 12067481 | Array-integrated upstream/downstream router for circuit switched parallel connectivity | — | 2024-08-20 |
| 12050997 | Row-by-row convolutional neural network mapping for analog artificial intelligence network training | HsinYu Tsai, Pritish Narayanan, Malte Johannes Rasch | 2024-07-30 |
| 12045612 | Special-purpose digital-compute hardware for efficient element-wise aggregation, scaling and offset | Shubham Jain, Milos Stanisavljevic, Yasuteru Kohda | 2024-07-23 |
| 12019590 | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks | Pritish Narayanan | 2024-06-25 |
| 11915132 | Synaptic weight transfer between conductance pairs with polarity inversion for reducing fixed device asymmetries | — | 2024-02-27 |
| 11868893 | Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference | HsinYu Tsai, Pritish Narayanan | 2024-01-09 |
| 11823740 | Selective application of multiple pulse durations to crossbar arrays | Masatoshi Ishii, Pritish Narayanan, Paul M. Solomon | 2023-11-21 |
| 11797833 | Competitive machine learning accuracy on neuromorphic arrays with non-ideal non-volatile memory devices | Pritish Narayanan | 2023-10-24 |
| 11580373 | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks | Pritish Narayanan | 2023-02-14 |
| 11562240 | Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference | HsinYu Tsai, Pritish Narayanan | 2023-01-24 |
| 11488664 | Distributing device array currents across segment mirrors | Charles Mackin, Pritish Narayanan | 2022-11-01 |
| 11461640 | Mitigation of conductance drift in neural network resistive processing units | HsinYu Tsai, Stefano Ambrogio, Pierce I-Jen Chuang, Pritish Narayanan | 2022-10-04 |
| 11436479 | System and method for transfer of analog synaptic weight information onto neuromorphic arrays with non-ideal non-volatile memory device | Pritish Narayanan | 2022-09-06 |
| 11347999 | Closed loop programming of phase-change memory | Stefano Ambrogio, Charles Mackin, HsinYu Tsai, Pritish Narayanan | 2022-05-31 |
| 11270194 | System and method for constructing synaptic weights for artificial neural networks from signed analog conductance-pairs of varying significance | — | 2022-03-08 |
| 11183238 | Suppressing outlier drift coefficients while programming phase change memory synapses | — | 2021-11-23 |
| 11182673 | Temporal memory adapted for single-shot learning and disambiguation of multiple predictions | Pritish Narayanan | 2021-11-23 |
| 11074499 | Synaptic weight transfer between conductance pairs with polarity inversion for reducing fixed device asymmetries | — | 2021-07-27 |
| 11038520 | Analog-to-digital conversion with reconfigurable function mapping for neural networks activation function acceleration | Pritish Narayanan, Giorgio Cristiano, Massimo Giordano | 2021-06-15 |
| 10896370 | Triage of training data for acceleration of large-scale machine learning | — | 2021-01-19 |
| 10726331 | Neural network circuits providing early integration before analog-to-digital conversion | — | 2020-07-28 |