Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12255656 | Split pulse width modulation to reduce crossbar array integration time | Geoffrey Burr, Masatoshi Ishii | 2025-03-18 |
| 12050997 | Row-by-row convolutional neural network mapping for analog artificial intelligence network training | HsinYu Tsai, Geoffrey Burr, Malte Johannes Rasch | 2024-07-30 |
| 12019590 | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks | Geoffrey Burr | 2024-06-25 |
| 12003240 | Analog memory-based complex multiply-accumulate (MACC) compute engine | Charles Mackin | 2024-06-04 |
| 11977974 | Compression of fully connected / recurrent layers of deep network(s) through enforcing spatial locality to weight matrices and effecting frequency compression | Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Suyog Gupta | 2024-05-07 |
| 11868893 | Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference | HsinYu Tsai, Geoffrey Burr | 2024-01-09 |
| 11823740 | Selective application of multiple pulse durations to crossbar arrays | Geoffrey Burr, Masatoshi Ishii, Paul M. Solomon | 2023-11-21 |
| 11797833 | Competitive machine learning accuracy on neuromorphic arrays with non-ideal non-volatile memory devices | Geoffrey Burr | 2023-10-24 |
| 11646944 | Configuring computing nodes in a three-dimensional mesh topology | Alexis Asseman, Ahmet S. Ozcan, Charles E. Cox, Nicolas Antoine | 2023-05-09 |
| 11580373 | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks | Geoffrey Burr | 2023-02-14 |
| 11562240 | Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference | HsinYu Tsai, Geoffrey Burr | 2023-01-24 |
| 11514981 | Programming devices and weights in hardware | Stefano Ambrogio | 2022-11-29 |
| 11488664 | Distributing device array currents across segment mirrors | Charles Mackin, Geoffrey Burr | 2022-11-01 |
| 11461640 | Mitigation of conductance drift in neural network resistive processing units | HsinYu Tsai, Stefano Ambrogio, Pierce I-Jen Chuang, Geoffrey Burr | 2022-10-04 |
| 11436479 | System and method for transfer of analog synaptic weight information onto neuromorphic arrays with non-ideal non-volatile memory device | Geoffrey Burr | 2022-09-06 |
| 11386320 | Magnetic domain wall-based non-volatile, linear and bi-directional synaptic weight element | Aakash Pushp | 2022-07-12 |
| 11347999 | Closed loop programming of phase-change memory | Stefano Ambrogio, Geoffrey Burr, Charles Mackin, HsinYu Tsai | 2022-05-31 |
| 11182673 | Temporal memory adapted for single-shot learning and disambiguation of multiple predictions | Geoffrey Burr | 2021-11-23 |
| 11184245 | Configuring computing nodes in a three-dimensional mesh topology | Alexis Asseman, Ahmet S. Ozcan, Charles E. Cox, Nicolas Antoine | 2021-11-23 |
| 11056185 | Apparatus for deep learning operations on resistive crossbar array | Scott C. Lewis | 2021-07-06 |
| 11038520 | Analog-to-digital conversion with reconfigurable function mapping for neural networks activation function acceleration | Giorgio Cristiano, Massimo Giordano, Geoffrey Burr | 2021-06-15 |
| 10692573 | Controlling aggregate signal amplitude from device arrays by segmentation and time-gating | Geoffrey Burr | 2020-06-23 |
| 10453528 | Controlling aggregate signal amplitude from device arrays by segmentation and time-gating | Geoffrey Burr | 2019-10-22 |
| 10423877 | High memory bandwidth neuromorphic computing system | Charles E. Cox, Harald Huels, Arvind Kumar, Ahmet S. Ozcan, J. Campbell Scott +1 more | 2019-09-24 |