Issued Patents All Time
Showing 26–50 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10395977 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert | 2019-08-27 |
| 10361153 | Surface nitridation in metal interconnects | Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang | 2019-07-23 |
| 10340180 | Merge mandrel features | Hsueh-Chung Chen, Martin O'Toole, Jason E. Stephens | 2019-07-02 |
| 10256185 | Nitridization for semiconductor structures | Lawrence A. Clevenger, Roger A. Quon, Hosadurga Shobha, Wei Wang, Chih-Chao Yang | 2019-04-09 |
| 10192780 | Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks | Xiaohan Wang, Jiehui Shu, Brendan O'Brien, Jinping Liu, Ravi Prakash Srivastava | 2019-01-29 |
| 10157789 | Via formation using sidewall image transfer process to define lateral dimension | Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie Mignot, Yann Mignot +3 more | 2018-12-18 |
| 10128147 | Interconnect structure | Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang | 2018-11-13 |
| 10068846 | Surface nitridation in metal interconnects | Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang | 2018-09-04 |
| 10014255 | Contacts having a geometry to reduce resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2018-07-03 |
| 9997408 | Method of optimizing wire RC for device performance and reliability | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, John E. Sheets, II | 2018-06-12 |
| 9953864 | Interconnect structure | Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang | 2018-04-24 |
| 9899317 | Nitridization for semiconductor structures | Lawrence A. Clevenger, Roger A. Quon, Hosadurga Shobha, Wei Wang, Chi-Chao Yang | 2018-02-20 |
| 9887160 | Multiple pre-clean processes for interconnect fabrication | Wei Wang, Chih-Chao Yang | 2018-02-06 |
| 9837309 | Semiconductor via structure with lower electrical resistance | Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang | 2017-12-05 |
| 9831182 | Multiple pre-clean processes for interconnect fabrication | Wei Wang, Chih-Chao Yang | 2017-11-28 |
| 9799552 | Low resistance metal contacts to interconnects | Stephen M. Gates, Gregory M. Fritz, Eric A. Joseph | 2017-10-24 |
| 9786550 | Low resistance metal contacts to interconnects | Stephen M. Gates, Gregory M. Fritz, Eric A. Joseph | 2017-10-10 |
| 9786603 | Surface nitridation in metal interconnects | Lawrence A. Clevenger, Roger A. Quon, Wei Wang, Chih-Chao Yang | 2017-10-10 |
| 9768113 | Self aligned via in integrated circuit | Yannick Feurprier, Joe Lee, Lars Liebmann, Yann Mignot, Douglas M. Trickett +1 more | 2017-09-19 |
| 9659820 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +2 more | 2017-05-23 |
| 9658523 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +1 more | 2017-05-23 |
| 9548243 | Self aligned via and pillar cut for at least a self aligned double pitch | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Theodorus E. Standaert | 2017-01-17 |
| 9490168 | Via formation using sidewall image transfer process to define lateral dimension | Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie Mignot, Yann Mignot +3 more | 2016-11-08 |
| 9466563 | Interconnect structure for an integrated circuit and method of fabricating an interconnect structure | Yann Mignot, James J. Kelly | 2016-10-11 |
| 9391020 | Interconnect structure having large self-aligned vias | John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard S. Wise +2 more | 2016-07-12 |