Issued Patents All Time
Showing 51–60 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8316335 | Multistage, hybrid synthesis processing facilitating integrated circuit layout | Harold Mielich, Friedrich Schroeder, Alexander Woerner | 2012-11-20 |
| 8255726 | Zero indication forwarding for floating point unit power reduction | Maarten J. Boersma, Silvia M. Mueller, Tim Niggemeier, Jochen Preiss | 2012-08-28 |
| 8253234 | Optimized semiconductor packaging in a three-dimensional stack | Thomas J. Brunschwiler, Hubert Harrer, Andreas Huber, Bruno Michel, Tim Niggemeier +2 more | 2012-08-28 |
| 8245065 | Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full | Tim Niggemeier, Maarten J. Boersma, Gunnar Spiess | 2012-08-14 |
| 7849428 | Formally deriving a minimal clock-gating scheme | J. Adam Butts, Tobias Gemmeke, Nicolas Maeding, Viresh Paruthi | 2010-12-07 |
| 7694112 | Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation | J. Adam Butts, Stephen V. Kosonocky, Silvia M. Mueller, Jochen Preiss | 2010-04-06 |
| 7509511 | Reducing register file leakage current within a processor | Tobias Gemmeke, Jens Leenstra, Tim Niggemeier | 2009-03-24 |
| 7502918 | Method and system for data dependent performance increment and power reduction | Tobias Gemmeke, Tim Niggemeier, Thomas Pflueger | 2009-03-10 |
| 6986027 | Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme | Rolf Hilgendorf | 2006-01-10 |
| 6968476 | Checkpointing a superscalar, out-of-order processor for error recovery | Hartmut Schwermer, Hans-Werner Tast | 2005-11-22 |