| 9886395 |
Evicting cached stores |
Uwe Brandt, Willm Hinrichs, Martin Recktenwald, Hans-Werner Tast |
2018-02-06 |
| 9658967 |
Evicting cached stores |
Uwe Brandt, Willm Hinrichs, Martin Recktenwald, Hans-Werner Tast |
2017-05-23 |
| 9588893 |
Store cache for transactional memory |
Uwe Brandt, Willm Hinrichs, Martin Recktenwald, Hans-Werner Tast |
2017-03-07 |
| 9588894 |
Store cache for transactional memory |
Uwe Brandt, Willm Hinrichs, Martin Recktenwald, Hans-Werner Tast |
2017-03-07 |
| 8891279 |
Enhanced wiring structure for a cache supporting auxiliary data output |
Christian Habermann, Martin Recktenwald, Hans-Werner Tast |
2014-11-18 |
| 7466716 |
Reducing latency in a channel adapter by accelerated I/O control block processing |
Rainer Dorsch, Martin Eckert, Markus Helms, Thomas Schlipf, Daniel Sentler +1 more |
2008-12-16 |
| 6182174 |
Memory card interface method using multiplexed storage protect key to indicate command acceptance |
Kevin W. Kark, William Wu Shen, Russell W. Lavallee, Udo Wille, Hartmut Ulland |
2001-01-30 |
| 5768294 |
Memory implemented error detection and correction code capable of detecting errors in fetching data from a wrong address |
Chin-Long Chen, Mu-Yue Hsiao, William Wu Shen |
1998-06-16 |
| 5761221 |
Memory implemented error detection and correction code using memory modules |
Klaus Ruediger Baat, Chin-Long Chen, Mu-Yue Hsiao, William Wu Shen |
1998-06-02 |
| 5751745 |
Memory implemented error detection and correction code with address parity bits |
Chin-Long Chen, Mu-Yue Hsiao, William Wu Shen |
1998-05-12 |
| 5691996 |
Memory implemented error detection and correction code with address parity bits |
Chin-Long Chen, Mu-Yue Hsiao, William Wu Shen |
1997-11-25 |
