Issued Patents All Time
Showing 26–50 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9645904 | Dynamic cache row fail accumulation due to catastrophic failure | Patrick J. Meaney, Arthur J. O'Neill | 2017-05-09 |
| 9600360 | Dynamic partial blocking of a cache ECC bypass | Pak-kin Mak, Arthur J. O'Neill, Deanna Postles Dunn Berger | 2017-03-21 |
| 9600361 | Dynamic partial blocking of a cache ECC bypass | Pak-kin Mak, Arthur J. O'Neill, Deanna Postles Dunn Berger | 2017-03-21 |
| 9594689 | Designated cache data backup during system operation | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill +1 more | 2017-03-14 |
| 9535787 | Dynamic cache row fail accumulation due to catastrophic failure | Patrick J. Meaney, Arthur J. O'Neill | 2017-01-03 |
| 9507660 | Eliminate corrupted portions of cache during runtime | Ekaterina M. Ambroladze, Michael A. Blake, Arthur J. O'Neill | 2016-11-29 |
| 9501283 | Cross-pipe serialization for multi-pipeline processor | Deanna Postles Dunn Berger, Edward J. Kaminski, Jr., Diane L. Orf | 2016-11-22 |
| 9477613 | Position-based replacement policy for address synonym management in shared caches | Deanna Postles Dunn Berger, Arthur O'Neil, Robert J. Sonnelitter, III | 2016-10-25 |
| 9459951 | Dynamic cache row fail accumulation due to catastrophic failure | Patrick J. Meaney, Arthur J. O'Neill | 2016-10-04 |
| 9378023 | Cross-pipe serialization for multi-pipeline processor | Deanna Postles Dunn Berger, Edward J. Kaminski, Jr., Diane L. Orf | 2016-06-28 |
| 9348524 | Memory controlled operations under dynamic relocation of storage | Timothy C. Bronson, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2016-05-24 |
| 9298468 | Monitoring processing time in a shared pipeline | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diana L. Orf +1 more | 2016-03-29 |
| 9189415 | EDRAM refresh in a high performance cache architecture | Arthur J. O'Neill, Robert J. Sonnelitter, III | 2015-11-17 |
| 9158694 | Mitigating busy time in a high performance cache | Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diana L. Orf, Robert J. Sonnelitter, III | 2015-10-13 |
| 9128788 | Managing quiesce requests in a multi-processor environment | Deanna Postles Dunn Berger | 2015-09-08 |
| 9104513 | Managing quiesce requests in a multi-processor environment | Deanna Postles Dunn Berger | 2015-08-11 |
| 9104581 | eDRAM refresh in a high performance cache architecture | Arthur J. O'Neill, Robert J. Sonnelitter, III | 2015-08-11 |
| 9104583 | On demand allocation of cache buffer slots | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Christine C. Jones, Diana L. Orf | 2015-08-11 |
| 9086990 | Bitline deletion | Ekaterina M. Ambroladze, Michael A. Blake, Hieu T. Huynh, Patrick J. Meaney, Arthur J. O'Neill | 2015-07-21 |
| 9075727 | Reducing penalties for cache accessing operations | Christine C. Jones, Arthur J. O'Neill, Diane L. Orf | 2015-07-07 |
| 9047199 | Reducing penalties for cache accessing operations | Christine C. Jones, Arthur J. O'Neill, Diane L. Orf | 2015-06-02 |
| 9037806 | Reducing store operation busy times | Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diane L. Orf | 2015-05-19 |
| 9015423 | Reducing store operation busy times | Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diane L. Orf | 2015-04-21 |
| 8996819 | Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy | Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2015-03-31 |
| 8930628 | Managing in-line store throughput reduction | Deanna Postles Dunn Berger, Christine C. Jones, Diana L. Orf, Robert J. Sonnelitter, III | 2015-01-06 |