Issued Patents All Time
Showing 51–75 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8788891 | Bitline deletion | Ekaterina M. Ambroladze, Michael A. Blake, Hieu T. Huynh, Patrick J. Meaney, Arthur J. O'Neill | 2014-07-22 |
| 8706972 | Dynamic mode transitions for cache instructions | Deanna Postles Dunn Berger, Kenneth D. Klapproth, Robert J. Sonnelitter, III | 2014-04-22 |
| 8671267 | Monitoring processing time in a shared pipeline | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diana L. Orf +1 more | 2014-03-11 |
| 8645796 | Dynamic pipeline cache error correction | Ekaterina M. Ambroladze, Edward T. Gerchman, Arthur J. O'Neill | 2014-02-04 |
| 8645642 | Tracking dynamic memory reallocation using a single storage address configuration table | Michael A. Blake, Pak-kin Mak, Mark S. Farrell | 2014-02-04 |
| 8645628 | Dynamically supporting variable cache array busy and access times for a targeted interleave | Deanna Postles Dunn Berger, Arthur J. O'Neill | 2014-02-04 |
| 8639887 | Dynamically altering a pipeline controller mode based on resource availability | Deanna Postles Dunn Berger, Kenneth D. Klapproth, Robert J. Sonnelitter, III | 2014-01-28 |
| 8635409 | Dynamic mode transitions for cache instructions | Deanna Postles Dunn Berger, Kenneth D. Klapproth, Robert J. Sonnelitter, III | 2014-01-21 |
| 8566532 | Management of multipurpose command queues in a multilevel cache hierarchy | Deanna Postles Dunn Berger, Garrett M. Drapala, Robert J. Sonnelitter, III | 2013-10-22 |
| 8560767 | Optimizing EDRAM refresh rates in a high performance cache architecture | Timothy C. Bronson, Arthur J. O'Neill, Scott Barnett Swaney | 2013-10-15 |
| 8539190 | Preemptive in-pipeline store compare resolution | Deanna Postles Dunn Berger, Robert J. Sonnelitter, III | 2013-09-17 |
| 8522076 | Error detection and recovery in a shared pipeline | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Diana L. Orf, Robert J. Sonnelitter, III | 2013-08-27 |
| 8521960 | Mitigating busy time in a high performance cache | Deanna Postles Dunn Berger, Christine C. Jones, Arthur J. O'Neill, Diana L. Orf, Robert J. Sonnelitter, III | 2013-08-27 |
| 8499144 | Updating settings of a processor core concurrently to the operation of a multi core processor system | Christopher R. Conklin, Adolf Martens, Walter Niklaus, Scott Barnett Swaney, Tobias Webel | 2013-07-30 |
| 8495287 | Clock-based debugging for embedded dynamic random access memory element in a processor core | Adam B. Collura, Arthur J. O'Neill, Gerard M. Salem, Robert J. Sonnelitter, III | 2013-07-23 |
| 8495452 | Handling corrupted background data in an out of order execution environment | Christian Habermann, Christian Jacobi, Diana L. Orf, Martin Recktenwald, Hans-Werner Tast +1 more | 2013-07-23 |
| 8468536 | Multiple level linked LRU priority | Deanna Postles Dunn Berger, Ekaterina M. Ambroladze, Diana L. Orf | 2013-06-18 |
| 8468421 | Memory system for error checking fetch and store data | Arthur J. O'Neill | 2013-06-18 |
| 8447932 | Recover store data merging | Deanna Postles Dunn Berger, Christine C. Jones, Diana L. Orf, Robert J. Sonnelitter, III | 2013-05-21 |
| 8447930 | Managing in-line store throughput reduction | Deanna Postles Dunn Berger, Christine C. Jones, Diana L. Orf, Robert J. Sonnelitter, III | 2013-05-21 |
| 8407442 | Preemptive in-pipeline store compare resolution | Deanna Postles Dunn Berger, Robert J. Sonnelitter, III | 2013-03-26 |
| 8407420 | System, apparatus and method utilizing early access to shared cache pipeline for latency reduction | Deanna Postles Dunn Berger, Robert J. Sonnelitter, III | 2013-03-26 |
| 8392621 | Managing dataflow in a temporary memory | Ekaterina M. Ambroladze, Deanna Postles Dunn Berger, Arthur J. O'Neill, Diana L. Orf, Robert J. Sonnelitter, III | 2013-03-05 |
| 8352687 | Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy | Deanna Postles Dunn Berger, Arthur J. O'Neill, Robert J. Sonnelitter, III | 2013-01-08 |
| 8327070 | Method for optimizing sequential data fetches in a computer system | Ekaterina M. Ambroladze, Arthur J. O'Neill | 2012-12-04 |