Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11221794 | Memory array element sparing | Hieu T. Huynh, Kenneth D. Klapproth | 2022-01-11 |
| 11048427 | Evacuation of memory from a drawer in a live multi-node system | Jason D. Kohl, Hieu T. Huynh, Michael A. Blake | 2021-06-29 |
| 10915461 | Multilevel cache eviction management | Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig R. Walters, Kevin Lopes +4 more | 2021-02-09 |
| 10901902 | Efficient inclusive cache management | Chad G. Wilson, Robert J. Sonnelitter, III, Ekaterina M. Ambroladze, Hieu T. Huynh, Jason D. Kohl +1 more | 2021-01-26 |
| 10831661 | Coherent cache with simultaneous data requests in same addressable index | Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Deanna Postles Dunn Berger, Chad G. Wilson, Kenneth D. Klapproth +3 more | 2020-11-10 |
| 10802966 | Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelization | Arun Kwangil Iyengar, Michael A. Blake, Vesselina K. Papazova, Arthur J. O'Neill, Jason D. Kohl +1 more | 2020-10-13 |
| 9003125 | Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index | Ekaterina M. Ambroladze, Michael A. Blake, Garrett M. Drapala, Pak-kin Mak, Arthur J. O'Neill | 2015-04-07 |