Issued Patents All Time
Showing 51–75 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6760809 | Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2004-07-06 |
| 6760817 | Method and system for prefetching utilizing memory initiated prefetch write operations | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2004-07-06 |
| 6754782 | Decentralized global coherency management in a multi-node computer system | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2004-06-22 |
| 6748518 | Multi-level multiprocessor speculation mechanism | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2004-06-08 |
| 6728873 | System and method for providing multiprocessor speculation within a speculative branch path | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2004-04-27 |
| 6725340 | Mechanism for folding storage barrier operations in a multiprocessor system | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2004-04-20 |
| 6721856 | Enhanced cache management mechanism via an intelligent system bus monitor | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2004-04-13 |
| 6721853 | High performance data processing system via cache victimization protocols | Guy L. Guthrie, Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2004-04-13 |
| 6711652 | Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2004-03-23 |
| 6704843 | Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2004-03-09 |
| 6701416 | Cache coherency protocol with tagged intervention of modified values | Ravi Kumar Arimilli, Jerry Don Lewis | 2004-03-02 |
| 6691220 | Multiprocessor speculation mechanism via a barrier speculation flag | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2004-02-10 |
| 6662275 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-12-09 |
| 6662216 | Fixed bus tags for SMP buses | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-12-09 |
| 6658536 | Cache-coherency protocol with recently read state for extending cache horizontally | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 2003-12-02 |
| 6658538 | Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-12-02 |
| 6654857 | Non-uniform memory access (NUMA) computer system having distributed global coherency management | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-11-25 |
| 6633959 | Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-10-14 |
| 6631450 | Symmetric multiprocessor address bus protocol with intra-cache line access information | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-10-07 |
| 6629209 | Cache coherency protocol permitting sharing of a locked data granule | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629210 | Intelligent cache management mechanism via processor access sequence analysis | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-09-30 |
| 6629212 | High speed lock acquisition mechanism with time parameterized cache coherency states | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6629214 | Extended cache coherency protocol with a persistent “lock acquired” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-30 |
| 6625660 | Multiprocessor speculation mechanism for efficiently managing multiple barrier operations | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2003-09-23 |
| 6625701 | Extended cache coherency protocol with a modified store instruction lock release indicator | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-09-23 |