Issued Patents All Time
Showing 76–100 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6615322 | Two-stage request protocol for accessing remote memory data in a NUMA data processing system | Ravi Kumar Arimilli, James Stephen Fields, Jr. | 2003-09-02 |
| 6615321 | Mechanism for collapsing store misses in an SMP computer system | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-09-02 |
| 6615320 | Store collapsing mechanism for SMP computer system | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-09-02 |
| 6609192 | System and method for asynchronously overlapping storage barrier operations with old and new storage operations | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2003-08-19 |
| 6606702 | Multiprocessor speculation mechanism with imprecise recycling of storage operations | Guy L. Guthrie, Ravi Kumar Arimilli, Derek E. Williams | 2003-08-12 |
| 6601144 | Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-07-29 |
| 6587926 | Incremental tag build for hierarchical memory architecture | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-07-01 |
| 6587925 | Elimination of vertical bus queueing within a hierarchical memory architecture | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-07-01 |
| 6587924 | Scarfing within a hierarchical memory architecture | Ravi Kumar Arimilli, Jerry Don Lewis | 2003-07-01 |
| 6581139 | Set-associative cache memory having asymmetric latency among sets | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2003-06-17 |
| 6574714 | Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-06-03 |
| 6571322 | Multiprocessor computer system with sectored cache line mechanism for cache intervention | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-05-27 |
| 6553462 | Multiprocessor computer system with sectored cache line mechanism for load and store operations | Ravi Kumar Arimilli, Guy L. Guthrie | 2003-04-22 |
| 6553442 | Bus master for SMP execution of global operations utilizing a single token with implied release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2003-04-22 |
| 6549989 | Extended cache coherency protocol with a “lock released” state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2003-04-15 |
| 6532521 | Mechanism for high performance transfer of speculative request data between levels of cache hierarchy | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-03-11 |
| 6516368 | Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2003-02-04 |
| 6510494 | Time based mechanism for cached speculative data deallocation | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2003-01-21 |
| 6507880 | Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2003-01-14 |
| 6505277 | Method for just-in-time delivery of load data by intervening caches | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Jerry Don Lewis | 2003-01-07 |
| 6502168 | Cache having virtual cache controller queues | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-12-31 |
| 6502171 | Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2002-12-31 |
| 6496921 | Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2002-12-17 |
| 6487637 | Method and system for clearing dependent speculations from a request queue | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, William J. Starke | 2002-11-26 |
| 6484241 | Multiprocessor computer system with sectored cache line system bus protocol mechanism | Ravi Kumar Arimilli, Guy L. Guthrie | 2002-11-19 |