JD

John Steven Dodson

IBM: 238 patents #119 of 70,183Top 1%
🗺 Texas: #55 of 125,132 inventorsTop 1%
Overall (All Time): #2,261 of 4,157,543Top 1%
238
Patents All Time

Issued Patents All Time

Showing 126–150 of 238 patents

Patent #TitleCo-InventorsDate
6397320 Method for just-in-time delivery of load data via cycle of dependency Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis 2002-05-28
6397300 High performance store instruction management via imprecise local cache update mechanism Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie 2002-05-28
6393528 Optimized cache allocation algorithm for multiple speculative requests Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. 2002-05-21
6393553 Acknowledgement mechanism for just-in-time delivery of load data Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis 2002-05-21
6389529 Method for alternate preferred time delivery of load data Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis 2002-05-14
6385702 High performance multiprocessor system with exclusive-deallocate cache state Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke 2002-05-07
6385694 High performance load instruction management via system bus with explicit register load and/or cache reload protocols Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie 2002-05-07
6374333 Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke 2002-04-16
6374330 Cache-coherency protocol with upstream undefined state Ravi Kumar Arimilli, Jerry Don Lewis 2002-04-16
6360299 Extended cache state with prefetched stream ID information Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. 2002-03-19
6353875 Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis 2002-03-05
6349367 Method and system for communication in which a castout operation is cancelled in response to snoop responses Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis 2002-02-19
6349369 Protocol for transferring modified-unsolicited state during data intervention Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke 2002-02-19
6347363 Merged vertical cache controller mechanism with combined cache controller and snoop queries for in-line caches Ravi Kumar Arimilli, Jerry Don Lewis 2002-02-12
6347361 Cache coherency protocols with posted operations Ravi Kumar Arimilli, Jerry Don Lewis 2002-02-12
6345343 Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke 2002-02-05
6345340 Cache coherency protocol with ambiguous state for posted operations Ravi Kumar Arimilli, Jerry Don Lewis 2002-02-05
6345344 Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke 2002-02-05
6345342 Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke 2002-02-05
6345339 Pseudo precise I-cache inclusivity for vertical caches Ravi Kumar Arimilli 2002-02-05
6343344 System bus directory snooping mechanism for read/castout (RCO) address transaction Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis 2002-01-29
6343347 Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis 2002-01-29
6341336 Cache coherency protocol having tagged state used with cross-bars Ravi Kumar Arimilli, Jerry Don Lewis 2002-01-22
6338124 Multiprocessor system bus with system controller explicitly updating snooper LRU information Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis 2002-01-08
6334172 Cache coherency protocol with tagged state for modified values Ravi Kumar Arimilli, Jerry Don Lewis 2001-12-25