Issued Patents All Time
Showing 151–175 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6330643 | Cache coherency protocols with global and local posted operations | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-12-11 |
| 6324617 | Method and system for communicating tags of data access target and castout victim in a single data transfer | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-11-27 |
| 6321305 | Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-11-20 |
| 6321306 | High performance multiprocessor system with modified-unsolicited cache state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2001-11-20 |
| 6314498 | Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke | 2001-11-06 |
| 6292872 | Cache coherency protocol having hovering (H) and recent (R) states | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-09-18 |
| 6279086 | Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-08-21 |
| 6275908 | Cache coherency protocol including an HR state | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-08-14 |
| 6275909 | Multiprocessor system bus with system controller explicitly updating snooper cache state information | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2001-08-14 |
| 6272603 | Cache coherency protocol having hovering (H), recent (R), and tagged (T) states | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-08-07 |
| 6263407 | Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-07-17 |
| 6247098 | Cache coherency protocol with selectively implemented tagged state | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-06-12 |
| 6212616 | Even/odd cache directory mechanism | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-04-03 |
| 6212605 | Eviction override for larx-reserved addresses | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 2001-04-03 |
| 6195729 | Deallocation with cache update protocol (L2 evictions) | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-02-27 |
| 6192451 | Cache coherency protocol for a data processing system including a multi-level memory hierarchy | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-02-20 |
| 6192458 | High performance cache directory addressing scheme for variable cache sizes utilizing associativity | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-02-20 |
| 6185658 | Cache with enhanced victim selection using the coherency states of cache lines | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-02-06 |
| 6182201 | Demand-based issuance of cache operations to a system bus | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 2001-01-30 |
| 6178484 | DCBST with ICBI mechanism to maintain coherency of bifurcated data and instruction caches | Ravi Kumar Arimilli, Jerry Don Lewis | 2001-01-23 |
| 6175930 | Demand based sync bus operation | Ravi Kumar Arimilli, Derek E. Williams, Jerry Don Lewis | 2001-01-16 |
| 6173371 | Demand-based issuance of cache operations to a processor bus | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 2001-01-09 |
| 6157980 | Cache directory addressing scheme for variable cache sizes | Ravi Kumar Arimilli, Jerry Don Lewis | 2000-12-05 |
| 6145059 | Cache coherency protocols with posted operations and tagged coherency states | Ravi Kumar Arimilli, Jerry Don Lewis | 2000-11-07 |
| 6145057 | Precise method and system for selecting an alternative cache entry for replacement in response to a conflict between cache operation requests | Ravi Kumar Arimilli | 2000-11-07 |