Issued Patents All Time
Showing 201–225 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6018791 | Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states | Ravi Kumar Arimilli, Jerry Don Lewis | 2000-01-25 |
| 6006311 | Dynamic updating of repair mask used for cache defect avoidance | Ravi Kumar Arimilli, Jerry Don Lewis, Timothy M. Skergan | 1999-12-21 |
| 6000014 | Software-managed programmable congruence class caching mechanism | Ravi Kumar Arimilli, Leo James Clark, Jerry Don Lewis | 1999-12-07 |
| 5996049 | Cache-coherency protocol with recently read state for data and instructions | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 1999-11-30 |
| 5983322 | Hardware-managed programmable congruence class caching mechanism | Ravi Kumar Arimilli, Leo James Clark, Jerry Don Lewis | 1999-11-09 |
| 5978888 | Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels | Ravi Kumar Arimilli, Leo James Clark, Jerry Don Lewis | 1999-11-02 |
| 5978871 | Method of layering cache and architectural specific functions for operation splitting | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 1999-11-02 |
| 5974507 | Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm | Ravi Kumar Arimilli, Leo James Clark, Jerry Don Lewis | 1999-10-26 |
| 5963974 | Cache intervention from a cache line exclusively holding an unmodified value | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 1999-10-05 |
| 5958068 | Cache array defect functional bypassing using repair mask | Ravi Kumar Arimilli, Jerry Don Lewis, Timothy M. Skergan | 1999-09-28 |
| 5956503 | Method and system for front-end and back-end gathering of store instructions within a data-processing system | Ravi Kumar Arimilli, Jerry Don Lewis | 1999-09-21 |
| 5946709 | Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 1999-08-31 |
| 5943685 | Method of shared intervention via a single data provider among shared caches for SMP bus | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 1999-08-24 |
| 5943686 | Multiple cache directories for non-arbitration concurrent accessing of a cache memory | Ravi Kumar Arimilli, Jerry Don Lewis, Timothy M. Skergan | 1999-08-24 |
| 5943684 | Method and system of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system | Ravi Kumar Arimilli | 1999-08-24 |
| 5940611 | Method and system for front-end gathering of store instructions within a data-processing system | Ravi Kumar Arimilli, Jerry Don Lewis | 1999-08-17 |
| 5940856 | Cache intervention from only one of many cache lines sharing an unmodified value | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 1999-08-17 |
| 5940864 | Shared memory-access priorization method for multiprocessors using caches and snoop responses | Ravi Kumar Arimilli, John Michael Kaiser, Jerry Don Lewis | 1999-08-17 |
| 5935234 | Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 1999-08-10 |
| 5937172 | Apparatus and method of layering cache and architectural specific functions to permit generic interface definition | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 1999-08-10 |
| 5931924 | Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights | Ravi Kumar Arimilli, Jerry Don Lewis, Derek E. Williams | 1999-08-03 |
| 5924118 | Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system | Ravi Kumar Arimilli, Jerry Don Lewis | 1999-07-13 |
| 5924121 | Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles | Ravi Kumar Arimilli, Jerry Don Lewis | 1999-07-13 |
| 5913231 | Method and system for high speed memory address forwarding mechanism | Jerry Don Lewis, Ravi Kumar Arimilli | 1999-06-15 |
| 5909698 | Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory | Ravi Kumar Arimilli, Jerry Don Lewis | 1999-06-01 |