Issued Patents All Time
Showing 101–125 of 238 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6480975 | ECC mechanism for set associative cache array | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-11-12 |
| 6480915 | Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2002-11-12 |
| 6477613 | Cache index based system address bus | Ravi Kumar Arimilli, Guy L. Guthrie, Jody B. Joyner, Jerry Don Lewis | 2002-11-05 |
| 6470427 | Programmable agent and method for managing prefetch queues | Ravi Kumar Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2002-10-22 |
| 6463507 | Layered local cache with lower level cache updating upper and lower level cache directories | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-10-08 |
| 6460101 | Token manager for execution of global operations utilizing multiple tokens | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2002-10-01 |
| 6460100 | Bus snooper for SMP execution of global operations utilizing a single token with implied release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2002-10-01 |
| 6460117 | Set-associative cache memory having a mechanism for migrating a most recently used set | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2002-10-01 |
| 6460118 | Set-associative cache memory having incremental access latencies among sets | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, James Stephen Fields, Jr., Guy L. Guthrie | 2002-10-01 |
| 6446166 | Method for upper level cache victim selection management by a lower level cache | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-09-03 |
| 6442629 | Bus protocol and token manager for execution of global operations utilizing a single token with multiple operations with explicit release | Ravi Kumar Arimilli, Jody B. Joyner, Jerry Don Lewis | 2002-08-27 |
| 6438656 | Method and system for cancelling speculative cache prefetch requests | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, William J. Starke | 2002-08-20 |
| 6434667 | Layered local cache with imprecise reload mechanism | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-08-13 |
| 6434670 | Method and apparatus for efficiently managing caches with non-power-of-two congruence classes | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-08-13 |
| 6430683 | Processor and method for just-in-time delivery of load data via time dependency field | Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis | 2002-08-06 |
| 6427204 | Method for just in-time delivery of instructions in a data processing system | Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis | 2002-07-30 |
| 6425090 | Method for just-in-time delivery of load data utilizing alternating time intervals | Ravi Kumar Arimilli, Lakshminarayanan Baba Arimilli, Jerry Don Lewis | 2002-07-23 |
| 6421763 | Method for instruction extensions for a tightly coupled speculative request unit | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2002-07-16 |
| 6421762 | Cache allocation policy based on speculative request history | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, Guy L. Guthrie, James Stephen Fields, Jr. | 2002-07-16 |
| 6418513 | Queue-less and state-less layered local data cache mechanism | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-07-09 |
| 6418516 | Method and system for managing speculative requests in a multi-level memory hierarchy | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie, William J. Starke | 2002-07-09 |
| 6418514 | Removal of posted operations from cache operations queue | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-07-09 |
| 6415358 | Cache coherency protocol having an imprecise hovering (H) state for instructions and data | Ravi Kumar Arimilli, Jerry Don Lewis | 2002-07-02 |
| 6405285 | Layered local cache mechanism with split register load bus and cache load bus | Ravi Kumar Arimilli, Leo James Clark, Guy L. Guthrie | 2002-06-11 |
| 6397298 | Cache memory having a programmable cache replacement scheme | Ravi Kumar Arimilli, Guy L. Guthrie | 2002-05-28 |