Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11791978 | Systems and methods for preventing side-channel attacks | — | 2023-10-17 |
| 11783032 | Systems and methods for protecting cache and main-memory from flush-based attacks | — | 2023-10-10 |
| 10068639 | Out-of-place presetting based on indirection table | Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras | 2018-09-04 |
| 10019370 | Probabilistic associative cache | Bulent Abali, John Steven Dodson, Balaram Sinharoy | 2018-07-10 |
| 9846641 | Variability aware wear leveling | Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras | 2017-12-19 |
| 9424194 | Probabilistic associative cache | Bulent Abali, John Steven Dodson, Balaram Sinharoy | 2016-08-23 |
| 9218296 | Low-latency, low-overhead hybrid encryption scheme | Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano | 2015-12-22 |
| 9087612 | DRAM error detection, evaluation, and correction | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim +1 more | 2015-07-21 |
| 9058896 | DRAM refresh | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim +1 more | 2015-06-16 |
| 9037930 | Managing errors in a DRAM by weak cell encoding | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim +1 more | 2015-05-19 |
| 8914764 | Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits | Pradip Bose, Alper Buyuktosunoglu, John Darringer, Jeonghee Shin | 2014-12-16 |
| 8898544 | DRAM error detection, evaluation, and correction | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim +1 more | 2014-11-25 |
| 8887014 | Managing errors in a DRAM by weak cell encoding | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim +1 more | 2014-11-11 |
| 8874846 | Memory cell presetting for improved memory performance | Michele M. Franceschini, Ashish Jagmohan, John P. Karidis, Luis A. Lastras-Montano | 2014-10-28 |
| 8863068 | Current-aware floorplanning to overcome current delivery limitations in integrated circuits | Pradip Bose, Alper Buyuktosunoglu, John Darringer, Jeonghee Shin | 2014-10-14 |
| 8848471 | Method for optimizing refresh rate for DRAM | Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim +1 more | 2014-09-30 |
| 8826216 | Token-based current control to mitigate current delivery limitations in integrated circuits | Pradip Bose, Alper Buyuktosunoglu, John Darringer, Jeonghee Shin | 2014-09-02 |
| 8683418 | Adaptive workload based optimizations to mitigate current delivery limitations in integrated circuits | Pradip Bose, Alper Buyuktosunoglu, John Darringer, Jeonghee Shin | 2014-03-25 |
| 8656118 | Adaptive wear leveling via monitoring the properties of memory reference stream | Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano | 2014-02-18 |
| 8627008 | Memory access prediction | — | 2014-01-07 |
| 8458501 | Measuring data switching activity in a microprocessor | Pradip Bose, Alper Buyuktosunoglu, Christopher Gonzalez, Victor Zyuban | 2013-06-04 |
| 8417917 | Processor core stacking for efficient collaboration | Philip G. Emma, Eren Kursun, Vijayalakshmi Srinivasan | 2013-04-09 |
| 8356153 | Adaptive wear leveling via monitoring the properties of memory reference stream | Michele M. Franceschini, John P. Karidis, Luis A. Lastras-Montano | 2013-01-15 |
| 8285969 | Reducing broadcasts in multiprocessors | Khubaib Khubaib, Vijayalakshmi Srinivasan | 2012-10-09 |
| 8250303 | Adaptive linesize in a cache | Kerry Bernstein | 2012-08-21 |