Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399713 | Multiplication hardware block with adaptive fidelity control system | Ljubisa Bajic, Syed Gilani | 2025-08-26 |
| 12248430 | Overlay layer for network of processor cores | Davor Capalija, Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky +3 more | 2025-03-11 |
| 12067395 | Pre-staged instruction registers for variable length instruction set machine | Miles Robert Dooley, Rakesh Shaji Lal, Stanislav Sokorac | 2024-08-20 |
| 12050913 | Processing core with meta data actuated conditional graph execution | Ljubisa Bajic, Ivan Hamer | 2024-07-30 |
| 11599358 | Pre-staged instruction registers for variable length instruction set machine | Miles Robert Dooley, Rakesh Shaji Lal, Stanislav Sokorac | 2023-03-07 |
| 11301264 | Processing core with operation suppression based on contribution estimate | Ljubisa Bajic, Ivan Hamer, Syed Gilani | 2022-04-12 |
| 11113051 | Processing core with metadata actuated conditional graph execution | Ljubisa Bajic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov | 2021-09-07 |
| 10817293 | Processing core with metadata actuated conditional graph execution | Ljubisa Bajic, Ivan Hamer | 2020-10-27 |
| 10585679 | Processing core with operation suppression based on contribution estimate | Ljubisa Bajic, Ivan Hamer, Syed Gilani | 2020-03-10 |
| 10318317 | Processing core with operation suppression based on contribution estimate | Ljubisa Bajic, Ivan Hamer, Syed Gilani | 2019-06-11 |