Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12050913 | Processing core with meta data actuated conditional graph execution | Ljubisa Bajic, Milos Trajkovic | 2024-07-30 |
| 11301264 | Processing core with operation suppression based on contribution estimate | Ljubisa Bajic, Milos Trajkovic, Syed Gilani | 2022-04-12 |
| 11113051 | Processing core with metadata actuated conditional graph execution | Ljubisa Bajic, Milos Trajkovic, Lejla Bajic, Aleksandar Cejkov | 2021-09-07 |
| 10817293 | Processing core with metadata actuated conditional graph execution | Ljubisa Bajic, Milos Trajkovic | 2020-10-27 |
| 10585679 | Processing core with operation suppression based on contribution estimate | Ljubisa Bajic, Milos Trajkovic, Syed Gilani | 2020-03-10 |
| 10318317 | Processing core with operation suppression based on contribution estimate | Ljubisa Bajic, Milos Trajkovic, Syed Gilani | 2019-06-11 |
| 7594204 | Method and apparatus for performing layout-driven optimizations on field programmable gate arrays | Deshanand Singh, Paul McHardy, Chris G. Sanford, Gabriel Quan, Terry Borer +3 more | 2009-09-22 |
| 7257800 | Method and apparatus for performing logic replication in field programmable gate arrays | Deshanand Singh, Gabriel Quan, Terry Borer, Valavan Manohararajah, Paul McHardy +2 more | 2007-08-14 |
| 7197734 | Method and apparatus for designing systems using logic regions | Deshanand Singh, Terry Borer, Steven Caranci, Tim Vanderhoek, Jimmy Kuo +5 more | 2007-03-27 |