Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8661329 | Generation of readable hierarchical path identifiers | Mark Ari Teper, Przemek Guzy | 2014-02-25 |
| 8504970 | Method and apparatus for performing automated timing closure analysis for systems implemented on target devices | Shawn Malhotra, Mark Ari Teper, Ketan Padalia, Mark Bourgeault | 2013-08-06 |
| 8407645 | Graphical block-based design exploration tool | Alexander Grbic, Mark Ari Teper | 2013-03-26 |
| 7657857 | Performance visualization of delay in circuit design | Przemek Guzy | 2010-02-02 |
| 7197734 | Method and apparatus for designing systems using logic regions | Deshanand Singh, Terry Borer, Tim Vanderhoek, Ivan Hamer, Jimmy Kuo +5 more | 2007-03-27 |