Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11093672 | Method and apparatus for performing fast incremental physical design optimization | Junaid Asim Khan, Gabriel Quan, Scott James Brissenden, Ryan Fung | 2021-08-17 |
| 10635772 | Method and apparatus for performing fast incremental physical design optimization | Junaid Asim Khan, Gabriel Quan, Scott James Brissenden, Ryan Fung | 2020-04-28 |
| 10073941 | Method and apparatus for performing efficient incremental compilation | Ryan Fung | 2018-09-11 |
| 9658830 | Structures for LUT-based arithmetic in PLDs | David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan +1 more | 2017-05-23 |
| 9594859 | Apparatus and associated methods for parallelizing clustering and placement | Adrian Ludwin, Ryan Fung, Vaughn Betz | 2017-03-14 |
| 9569574 | Method and apparatus for performing fast incremental physical design optimization | Junaid Asim Khan, Gabriel Quan, Scott James Brissenden, Ryan Fung | 2017-02-14 |
| 8856713 | Method and apparatus for performing efficient incremental compilation | Ryan Fung | 2014-10-07 |
| 8788550 | Structures for LUT-based arithmetic in PLDs | David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan +1 more | 2014-07-22 |
| 8539418 | Method and apparatus for performing efficient incremental compilation | Ryan Fung | 2013-09-17 |
| 8504970 | Method and apparatus for performing automated timing closure analysis for systems implemented on target devices | Shawn Malhotra, Mark Ari Teper, Steven Caranci, Mark Bourgeault | 2013-08-06 |
| 8499273 | Systems and methods for optimizing placement and routing | Kimberley Anne Bozman, Ryan Fung, Vaughn Betz, David Neto | 2013-07-30 |
| 8281274 | Method and apparatus for performing efficient incremental compilation | Ryan Fung | 2012-10-02 |
| 7707532 | Techniques for grouping circuit elements into logic blocks | Kimberly Bozman, Vaughn Betz | 2010-04-27 |
| 7681165 | Apparatus and methods for congestion estimation and optimization for computer-aided design software | Jason Peters, Adrian Ludwin | 2010-03-16 |
| 7558812 | Structures for LUT-based arithmetic in PLDs | David Cashman, David Lewis, Andy L. Lee, Jay Schleicher, Jinyong Yuan +1 more | 2009-07-07 |
| 7493585 | Methods of packing user logical RAM into dedicated RAM blocks and dual-use logic/RAM blocks | Elias Ahmed | 2009-02-17 |
| 7441208 | Methods for designing integrated circuits | Vaughn Betz, Vadim Gouterman | 2008-10-21 |
| 7415682 | Automatic adjustment of optimization effort in configuring programmable devices | Jason Peters, Vaughn Betz | 2008-08-19 |
| 7370291 | Method for mapping logic design memory into physical memory devices of a programmable logic device | Ryan Fung | 2008-05-06 |
| 7275228 | Techniques for grouping circuit elements into logic blocks | Kimberly Bozman, Vaughn Betz | 2007-09-25 |
| 7268584 | Adder circuitry for a programmable logic device | David Cashman, David Lewis, Gregg William Baeckler | 2007-09-11 |
| 6871328 | Method for mapping logic design memory into physical memory device of a programmable logic device | Ryan Fung | 2005-03-22 |