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M/A for compiling parallel program having barrier synchronization for programmable hardware |
Deshanand Singh, Tomasz Czajkowski, John Stuart Freeman, Tian Yi David Han |
2020-03-24 |
| 10417362 |
Method and apparatus for deriving signal activities for power analysis and optimization |
Vaughn Betz, Jennifer Farrugia, Meghal Varia |
2019-09-17 |
| 9697309 |
Metastability-hardened synchronization circuit |
Ryan Fung, David Lewis |
2017-07-04 |
| 9342640 |
Method and apparatus for protecting, optimizing, and reporting synchronizers |
Ryan Fung, Vaughn Betz |
2016-05-17 |
| 9330733 |
Power-aware RAM processing |
Russell George Tessier, Vaughn Betz, Thiagaraja Golpalsamy |
2016-05-03 |
| 8898603 |
Method and apparatus for deriving signal activities for power analysis and optimization |
Vaughn Betz, Jennifer Farrugia, Meghal Varia |
2014-11-25 |
| 8732639 |
Method and apparatus for protecting, optimizing, and reporting synchronizers |
Ryan Fung, Vaughn Betz |
2014-05-20 |
| 8499273 |
Systems and methods for optimizing placement and routing |
Kimberley Anne Bozman, Ryan Fung, Vaughn Betz, Ketan Padalia |
2013-07-30 |
| 8250500 |
Method and apparatus for deriving signal activities for power analysis and optimization |
Vaughn Betz, Jennifer Farrugia, Meghal Varia |
2012-08-21 |
| 8015425 |
Power reduction techniques for components in integrated circuits |
Aaron Charles Egier |
2011-09-06 |
| 8001537 |
Method and apparatus for compiling programmable logic device configurations |
Mihail Iotov, Pouyan Djahani, David Karchmer, Kumara Tharmalingam |
2011-08-16 |
| 7877710 |
Method and apparatus for deriving signal activities for power analysis and optimization |
Vaughn Betz, Meghal Varia, Gregg William Baeckler |
2011-01-25 |
| 7877555 |
Power-aware RAM processing |
Russell George Tessier, Vaughn Betz, Thiagaraja Golpalsamy |
2011-01-25 |
| 7774729 |
Method and apparatus for reducing dynamic power in a system |
— |
2010-08-10 |
| 7587620 |
Power reduction techniques for components in integrated circuits by assigning inputs to a plurality of ports based on power consumption ratings |
Aaron Charles Egier |
2009-09-08 |
| 7555741 |
Computer-aided-design tools for reducing power consumption in programmable logic devices |
David Milton, Vaughn Betz |
2009-06-30 |
| 7545196 |
Clock distribution for specialized processing block in programmable logic device |
Michael D. Hutton, Kumara Tharmalingam, Yi-Wen Lin |
2009-06-09 |
| 6957412 |
Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements |
Vaughn Betz, Elias Ahmed |
2005-10-18 |