Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393756 | Methods and apparatus for profile-guided optimization of integrated circuits | Byron Sinclair | 2025-08-19 |
| 11675948 | Methods and apparatus for profile-guided optimization of integrated circuits | Byron Sinclair | 2023-06-13 |
| 10997339 | Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification | Byron Sinclair, Dirk Seynhaeve | 2021-05-04 |
| 10599404 | M/A for compiling parallel program having barrier synchronization for programmable hardware | David Neto, Deshanand Singh, Tomasz Czajkowski, Tian Yi David Han | 2020-03-24 |
| 10437743 | Interface circuitry for parallel computing architecture circuits | Davor Capalija, Andrei Mihai Hagiescu Miriste, Alan Baker | 2019-10-08 |
| 10120969 | Global variable optimization for integrated circuit applications | Byron Sinclair, Andrew Chaang Ling | 2018-11-06 |
| 9922150 | Method and apparatus for satisfying operating conditions in a system design using an electronic design automation tool | Peter Yiannacouras, Deshanand Singh | 2018-03-20 |
| 9703696 | Guided memory buffer allocation | Peter Yiannacouras, Deshanand Singh | 2017-07-11 |
| 9547738 | Invariant code optimization in high-level FPGA synthesis | Dmitry N. Denisenko | 2017-01-17 |
| 9424043 | Forward-flow selection | Tomasz Czajkowski | 2016-08-23 |
| 9166597 | Integrated circuit processing via offload processor | Dmitry N. Denisenko | 2015-10-20 |
| 9135087 | Workgroup handling in pipelined circuits | Tomasz Czajkowski, Peter Yiannacouras | 2015-09-15 |
| 9117022 | Hierarchical arbitration | Gordon Raymond Chiu | 2015-08-25 |
| 8201114 | Method and apparatus for performing look up table unpacking and repacking for resynthesis | Valavan Manohararajah, Gordon Raymond Chiu | 2012-06-12 |
| 7720243 | Acoustic enhancement for behind the ear communication devices | Mark A. Brumback, Dustin L. Potter | 2010-05-18 |