Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367041 | Seamless place and route for heterogeneous network of processor cores | Jasmina Vasiljevic, Ljubisa Bajic, Stanislav Sokorac | 2025-07-22 |
| 12321855 | Graph execution using access request response dynamic batch assembly | Ljubisa Bajic, Ivan Matosevic, Alex Cejkov | 2025-06-03 |
| 12260197 | Sparsity uniformity enforcement for multicore processor | Ljubisa Bajic, Yu-Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati +4 more | 2025-03-25 |
| 12248430 | Overlay layer for network of processor cores | Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky, S. Alexander Chin +3 more | 2025-03-11 |
| 12236237 | Processor cores using content object identifiers for routing and computation | Ljubisa Bajic, Jasmina Vasiljevic, Yongbum Kim | 2025-02-25 |
| 12210478 | Overlay layer hardware unit for network of processor cores | Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin, Djordje Maksimovic +1 more | 2025-01-28 |
| 12118060 | Computational circuit with hierarchical accumulator | Ljubisa Bajic, Alex Cejkov | 2024-10-15 |
| 12019546 | Data structure optimized dedicated memory caches | Ljubisa Bajic, Ivan Matosevic, Alex Cejkov | 2024-06-25 |
| 11960885 | Seamless place and route for heterogenous network of processor cores | Jasmina Vasiljevic, Ljubisa Bajic, Stanislav Sokorac | 2024-04-16 |
| 11934897 | Application data flow graph execution using network-on-chip overlay | Jasmina Vasiljevic, Zahi Moudallal, Utku Aydonat, Joseph Chu, S. Alexander Chin +1 more | 2024-03-19 |
| 11829752 | Processor cores using packet identifiers for routing and computation | Ljubisa Bajic, Jasmina Vasiljevic | 2023-11-28 |
| 11734224 | Overlay layer hardware unit for network of processor cores | Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin, Djordje Maksimovic +1 more | 2023-08-22 |
| 11709662 | Sparsity uniformity enforcement for multicore processor | Ljubisa Bajic, Yu-Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati +4 more | 2023-07-25 |
| 11693639 | Sparsity uniformity enforcement for multicore processor | Ljubisa Bajic, Yu-Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati +4 more | 2023-07-04 |
| 11520701 | Data structure optimized dedicated memory caches | Ljubisa Bajic, Ivan Matosevic, Alex Cejkov | 2022-12-06 |
| 11467846 | Overlay layer for network of processor cores | Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky, S. Alexander Chin +1 more | 2022-10-11 |
| 11328037 | Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers | Jack Z. Yinger, Andrew Chaang Ling, Tomasz Czajkowski, Eriko Nurvitadhi, Deborah T. Marr | 2022-05-10 |
| 11269628 | Processor cores using packet identifiers for routing and computation | Ljubisa Bajic, Jasmina Vasiljevic | 2022-03-08 |
| 11074492 | Method and apparatus for performing different types of convolution operations with the same processing elements | Meghan Lele, Andrew Chaang Ling | 2021-07-27 |
| 10437743 | Interface circuitry for parallel computing architecture circuits | Andrei Mihai Hagiescu Miriste, John Stuart Freeman, Alan Baker | 2019-10-08 |
| 10339201 | Dot product based processing elements | Andrew Chaang Ling, Tomasz Czajkowski, Andrei Mihai Hagiescu Miriste | 2019-07-02 |
| 10049082 | Dot product based processing elements | Andrew Chaang Ling, Tomasz Czajkowski, Andrei Mihai Hagiescu Miriste | 2018-08-14 |