Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399713 | Multiplication hardware block with adaptive fidelity control system | Milos Trajkovic, Syed Gilani | 2025-08-26 |
| 12367041 | Seamless place and route for heterogeneous network of processor cores | Jasmina Vasiljevic, Davor Capalija, Stanislav Sokorac | 2025-07-22 |
| 12340185 | Processing core with data associative adaptive rounding | Alex Cejkov, Lejla Bajic | 2025-06-24 |
| 12321855 | Graph execution using access request response dynamic batch assembly | Davor Capalija, Ivan Matosevic, Alex Cejkov | 2025-06-03 |
| 12260197 | Sparsity uniformity enforcement for multicore processor | Davor Capalija, Yu-Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati +4 more | 2025-03-25 |
| 12248430 | Overlay layer for network of processor cores | Davor Capalija, Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky +3 more | 2025-03-11 |
| 12236237 | Processor cores using content object identifiers for routing and computation | Davor Capalija, Jasmina Vasiljevic, Yongbum Kim | 2025-02-25 |
| 12210478 | Overlay layer hardware unit for network of processor cores | Ivan Matosevic, Davor Capalija, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin +1 more | 2025-01-28 |
| 12118060 | Computational circuit with hierarchical accumulator | Davor Capalija, Alex Cejkov | 2024-10-15 |
| 12050913 | Processing core with meta data actuated conditional graph execution | Milos Trajkovic, Ivan Hamer | 2024-07-30 |
| 12039289 | Processing core with data associative adaptive rounding | Alex Cejkov, Lejla Bajic | 2024-07-16 |
| 12019546 | Data structure optimized dedicated memory caches | Davor Capalija, Ivan Matosevic, Alex Cejkov | 2024-06-25 |
| 11960885 | Seamless place and route for heterogenous network of processor cores | Jasmina Vasiljevic, Davor Capalija, Stanislav Sokorac | 2024-04-16 |
| 11936382 | Adaptive oscillator for clock generation | Joyce Cheuk Wai Wong, Dragoljub Ignjatovic, Mikhail Rodionov, Stephen V. Kosonocky, Steven J. Kommrusch | 2024-03-19 |
| 11934897 | Application data flow graph execution using network-on-chip overlay | Jasmina Vasiljevic, Davor Capalija, Zahi Moudallal, Utku Aydonat, Joseph Chu +1 more | 2024-03-19 |
| 11829752 | Processor cores using packet identifiers for routing and computation | Davor Capalija, Jasmina Vasiljevic | 2023-11-28 |
| 11734224 | Overlay layer hardware unit for network of processor cores | Ivan Matosevic, Davor Capalija, Jasmina Vasiljevic, Utku Aydonat, S. Alexander Chin +1 more | 2023-08-22 |
| 11709662 | Sparsity uniformity enforcement for multicore processor | Davor Capalija, Yu-Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati +4 more | 2023-07-25 |
| 11693639 | Sparsity uniformity enforcement for multicore processor | Davor Capalija, Yu-Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati +4 more | 2023-07-04 |
| 11645041 | Processing core with data associative adaptive rounding | Alex Cejkov, Lejla Bajic | 2023-05-09 |
| 11520701 | Data structure optimized dedicated memory caches | Davor Capalija, Ivan Matosevic, Alex Cejkov | 2022-12-06 |
| 11467846 | Overlay layer for network of processor cores | Davor Capalija, Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky +1 more | 2022-10-11 |
| 11301264 | Processing core with operation suppression based on contribution estimate | Milos Trajkovic, Ivan Hamer, Syed Gilani | 2022-04-12 |
| 11269628 | Processor cores using packet identifiers for routing and computation | Davor Capalija, Jasmina Vasiljevic | 2022-03-08 |
| 11245643 | Speculative resource allocation for routing on interconnect fabrics | Ivan Matosevic | 2022-02-08 |