Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Computer-aided-design tools for reducing power consumption in programmable logic devices

Computer-aided-design tools for reducing power consumption in programmable logic devices

US Patent 7555741 · Granted Jun 30, 2009

Estimated economic value: $14,977,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for performing parallel routing using a multi-threaded rout2023
Characterization of power delivery network in field programmable gate arrays or 2021
Method and apparatus for performing parallel routing using a multi-threaded rout2020
Method and apparatus for performing register retiming in the presence of false p2020
M/A for compiling parallel program having barrier synchronization for programmab2020
Method and apparatus for deriving signal activities for power analysis and optim2019
Method and apparatus for deriving signal activities for power analysis and optim2019
Method and apparatus for placing and routing partial reconfiguration modules2019
Method and apparatus for performing parallel routing using a multi-threaded rout2018
Method and apparatus for performing register retiming in the presence of false p2018
Implementing integrated circuit designs using depopulation and repopulation oper2017
Method and apparatus for implementing soft constraints in tools used for designi2017