| 9122826 |
Method and apparatus for performing compilation using multiple design flows |
Terry Borer, Andrew Leaver, Gabriel Quan, Stephen D. Brown |
2015-09-01 |
$43,351,000 |
| 8589838 |
M/A for performing incremental compilation using top-down and bottom-up design approaches |
Terry Borer, Andrew Leaver, Gabriel Quan, Stephen D. Brown |
2013-11-19 |
$6,038,000 |
| 8572530 |
Method and apparatus for performing path-level skew optimization and analysis for a logic design |
Ryan Fung, Vaughn Betz |
2013-10-29 |
$8,624,000 |
| 8516504 |
Method for adding device information by extending an application programming interface |
Jim Park |
2013-08-20 |
$7,537,000 |
| 8250505 |
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches |
Terry Borer, Andrew Leaver, Gabriel Quan, Stephen D. Brown |
2012-08-21 |
$17,072,000 |
| 8161469 |
Method and apparatus for comparing programmable logic device configurations |
Mihail Iotov, Erhard Joachim Pistorius, Jim Park |
2012-04-17 |
$12,323,000 |
| 8112728 |
Early timing estimation of timing statistical properties of placement |
Michael D. Hutton |
2012-02-07 |
$32,350,000 |
| 8001537 |
Method and apparatus for compiling programmable logic device configurations |
Mihail Iotov, David Neto, Pouyan Djahani, Kumara Tharmalingam |
2011-08-16 |
$9,115,000 |
| 7877721 |
Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits |
James Schleicher |
2011-01-25 |
$13,497,000 |
| 7853911 |
Method and apparatus for performing path-level skew optimization and analysis for a logic design |
Ryan Fung, Vaughn Betz |
2010-12-14 |
$31,320,000 |
| 7784008 |
Performance visualization system |
Michael D. Hutton, Zhiru Zhang |
2010-08-24 |
$10,041,000 |
| 7725856 |
Method and apparatus for performing parallel slack computation |
Jason Govig |
2010-05-25 |
$3,835,000 |
| 7669157 |
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches |
Terry Borer, Andrew Leaver, Gabriel Quan, Stephen D. Brown |
2010-02-23 |
$16,218,000 |
| 7587688 |
User-directed timing-driven synthesis |
Babette van Antwerpen, Jinyong Yuan |
2009-09-08 |
$3,731,000 |
| 7584443 |
Clock domain conflict analysis for timing graphs |
Jason Govig, William B. Davis |
2009-09-01 |
$10,001,000 |
| 7577929 |
Early timing estimation of timing statistical properties of placement |
Michael D. Hutton |
2009-08-18 |
$9,782,000 |
| 7464362 |
Method and apparatus for performing incremental compilation |
Terry Borer, Jason Govig, Andrew Leaver, Gabriel Quan, Kevin Chan +2 more |
2008-12-09 |
$8,318,000 |
| 7358766 |
Mask-programmable logic device with programmable portions |
Jimmy Lawson, Marwan A. Khalaf |
2008-04-15 |
$4,201,000 |
| 7275232 |
Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits |
James Schleicher |
2007-09-25 |
$7,011,000 |
| 7231337 |
Using assignment decision diagrams with control nodes for sequential review during behavioral simulation |
Daniel S. Stellenberg |
2007-06-12 |
$10,773,000 |
| 7064580 |
Mask-programmable logic device with programmable portions |
Jimmy Lawson, Marwan A. Khalaf |
2006-06-20 |
$6,360,000 |
| 6961690 |
Behaviorial digital simulation using hybrid control and data flow representations |
Daniel S. Stellenberg |
2005-11-01 |
$12,939,000 |
| 6697773 |
Using assignment decision diagrams with control nodes for sequential review during behavioral simulation |
Daniel S. Stellenberg |
2004-02-24 |
$83,749,000 |
| 6173245 |
Programmable logic array device design using parameterized logic modules |
Scott Redman, Jeffrey Chao-Nan Chen, James Schleicher |
2001-01-09 |
$134,612,000 |
| 6167364 |
Methods and apparatus for automatically generating interconnect patterns in programmable logic devices |
Daniel S. Stellenberg |
2000-12-26 |
$117,653,000 |
