BA

Babette van Antwerpen

IN Intel: 22 patents #1,785 of 30,777Top 6%
Overall (All Time): #196,631 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9230047 Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement Gregg William Baeckler 2016-01-05
9053274 Register retiming technique Michael D. Hutton, Gregg William Baeckler, Jinyong Yuan 2015-06-09
8954906 Method and apparatus for performing parallel synthesis on a field programmable gate array Gregg William Baeckler 2015-02-10
8806399 Register retiming technique Michael D. Hutton, Gregg William Baeckler, Jinyong Yuan 2014-08-12
8661380 Method and apparatus for performing parallel synthesis on a field programmable gate array Gregg William Baeckler 2014-02-25
8402408 Register retiming technique Michael D. Hutton, Gregg William Baeckler, Richard Yuan 2013-03-19
8166427 Tracing and reporting registers removed during synthesis Swatiben Ruturaj Pathak, Michael D. Hutton, Andrew Leaver 2012-04-24
8108812 Register retiming technique Michael D. Hutton, Gregg William Baeckler, Richard Yuan 2012-01-31
7945877 Recognizing muliplexers 2011-05-17
7689955 Register retiming technique Michael D. Hutton, Gregg William Baeckler, Richard Yuan 2010-03-30
7634705 Methods and apparatus for error checking code decomposition Gregg William Baeckler 2009-12-15
7594208 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Terry Borer, Ian Chesal, James Schleicher, David W. Mendel, Mike Hutton +7 more 2009-09-22
7587688 User-directed timing-driven synthesis Jinyong Yuan, David Karchmer 2009-09-08
7441212 State machine recognition and optimization Gregg William Baeckler 2008-10-21
7418690 Local searching techniques for technology mapping 2008-08-26
7415693 Method and apparatus for reducing synthesis runtime Gregg William Baeckler, Jinyong Yuan 2008-08-19
7337100 Physical resynthesis of a logic design Michael D. Hutton, Joachim Pistorius, Gregg William Baeckler, Richard Yuan, Yean-Yow Hwang 2008-02-26
7246340 Timing-driven synthesis with area trade-off Jinyon Yuan 2007-07-17
7224183 Fast method for functional mapping to incomplete LUT pairs Gregg William Baeckler 2007-05-29
7181703 Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Terry Borer, Ian Chesal, James Schleicher, David W. Mendel, Mike Hutton +7 more 2007-02-20
7171633 Estimating quality during early synthesis Yean-Yow Hwang, Richard Yuan 2007-01-30
7120883 Register retiming technique Michael D. Hutton, Gregg William Baeckler, Richard Yuan 2006-10-10