Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9658830 | Structures for LUT-based arithmetic in PLDs | Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher +1 more | 2017-05-23 |
| 9172378 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Michael D. Hutton, Gregg William Baeckler, Chris Wysocki, Pouyan Djahani | 2015-10-27 |
| 9053274 | Register retiming technique | Babette van Antwerpen, Michael D. Hutton, Gregg William Baeckler | 2015-06-09 |
| 8806399 | Register retiming technique | Babette van Antwerpen, Michael D. Hutton, Gregg William Baeckler | 2014-08-12 |
| 8788550 | Structures for LUT-based arithmetic in PLDs | Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher +1 more | 2014-07-22 |
| 8601424 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Michael D. Hutton, Gregg William Baeckler, Chris Wysocki, Pouyan Djahani | 2013-12-03 |
| 8443327 | Reassembling scattered logic blocks in integrated circuits | Mohd Mawardi Bin Mohd Razha | 2013-05-14 |
| 8397185 | Graphical user aid for technology migration and associated methods | Steven Perry, Shih-Yueh Lin, John R. Chase | 2013-03-12 |
| 8271821 | Flexible RAM clock enable | Christopher F. Lane, David Jefferson, Vaughn Betz | 2012-09-18 |
| 8245163 | Partial compilation of circuit design with new software version to obtain a complete compiled design | Ee Ling Ooi, Chai Pin Chew | 2012-08-14 |
| 8191020 | Graphical user aid for technology migration and associated methods | Steven Perry, Shih-Yueh Lin, John R. Chase | 2012-05-29 |
| 8006206 | Gated clock conversion | — | 2011-08-23 |
| 7992110 | Methods of verifying functional equivalence between FPGA and structured ASIC logic cells | Ji-Yong Park | 2011-08-02 |
| 7890910 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Michael D. Hutton, Gregg William Baeckler, Chris Wysocki, Pouyan Djahani | 2011-02-15 |
| 7725871 | SAT-based technology mapping framework | Sean Safarpour, Gregg William Baeckler | 2010-05-25 |
| 7705628 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers | Michael D. Hutton, Andy L. Lee, Gregg William Baeckler, Keith Duwel | 2010-04-27 |
| 7631284 | Graphical user aid for technology migration and associated methods | Steven Perry, Shih-Yueb Lin, John R. Chase | 2009-12-08 |
| 7587688 | User-directed timing-driven synthesis | Babette van Antwerpen, David Karchmer | 2009-09-08 |
| 7558812 | Structures for LUT-based arithmetic in PLDs | Ketan Padalia, David Cashman, David Lewis, Andy L. Lee, Jay Schleicher +1 more | 2009-07-07 |
| 7424689 | Gated clock conversion | — | 2008-09-09 |
| 7415693 | Method and apparatus for reducing synthesis runtime | Babette van Antwerpen, Gregg William Baeckler | 2008-08-19 |
| 7406668 | Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations | Bruce B. Pedersen | 2008-07-29 |
| 7397726 | Flexible RAM clock enable | Christopher F. Lane, David Jefferson, Vaughn Betz | 2008-07-08 |
| 7386819 | Methods of verifying functional equivalence between FPGA and structured ASIC logic cells | Ji-Yong Park | 2008-06-10 |
| 7386828 | SAT-based technology mapping framework | Sean Safarpour, Gregg William Baeckler | 2008-06-10 |