Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11093672 | Method and apparatus for performing fast incremental physical design optimization | Junaid Asim Khan, Ketan Padalia, Scott James Brissenden, Ryan Fung | 2021-08-17 |
| 10635772 | Method and apparatus for performing fast incremental physical design optimization | Junaid Asim Khan, Ketan Padalia, Scott James Brissenden, Ryan Fung | 2020-04-28 |
| 9754065 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Terry Borer, Stephen D. Brown, Deshanand Singh, Chris G. Sanford, Vaughn Betz +2 more | 2017-09-05 |
| 9569574 | Method and apparatus for performing fast incremental physical design optimization | Junaid Asim Khan, Ketan Padalia, Scott James Brissenden, Ryan Fung | 2017-02-14 |
| 9122826 | Method and apparatus for performing compilation using multiple design flows | Terry Borer, Andrew Leaver, David Karchmer, Stephen D. Brown | 2015-09-01 |
| 8589838 | M/A for performing incremental compilation using top-down and bottom-up design approaches | Terry Borer, Andrew Leaver, David Karchmer, Stephen D. Brown | 2013-11-19 |
| 8589849 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Terry Borer, Stephen D. Brown, Deshanand Singh, Chris G. Sanford, Vaughn Betz +2 more | 2013-11-19 |
| 8434044 | Specifying placement and routing constraints for security and redundancy | David Samuel Goldman, Bruce B. Pedersen, Yuen Ho Choi | 2013-04-30 |
| 8250505 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches | Terry Borer, Andrew Leaver, David Karchmer, Stephen D. Brown | 2012-08-21 |
| 7669157 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches | Terry Borer, Andrew Leaver, David Karchmer, Stephen D. Brown | 2010-02-23 |
| 7594204 | Method and apparatus for performing layout-driven optimizations on field programmable gate arrays | Deshanand Singh, Paul McHardy, Chris G. Sanford, Terry Borer, Ian Chesal +3 more | 2009-09-22 |
| 7464362 | Method and apparatus for performing incremental compilation | Terry Borer, David Karchmer, Jason Govig, Andrew Leaver, Kevin Chan +2 more | 2008-12-09 |
| 7360190 | Method and apparatus for performing retiming on field programmable gate arrays | Deshanand Singh, Terry Borer, Ian Chesal, Valavan Manohararajah, Karl Schabas +1 more | 2008-04-15 |
| 7257800 | Method and apparatus for performing logic replication in field programmable gate arrays | Deshanand Singh, Terry Borer, Valavan Manohararajah, Paul McHardy, Ivan Hamer +2 more | 2007-08-14 |
| 7194720 | Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices | Terry Borer, Stephen D. Brown, Deshanand Singh, Chris G. Sanford, Vaughn Betz +2 more | 2007-03-20 |
| 7181717 | Method and apparatus for placement of components onto programmable logic devices | Deshanand Singh, Stephen D. Brown, Terry Borer, Chris G. Sanford | 2007-02-20 |
| 6779169 | Method and apparatus for placement of components onto programmable logic devices | Deshanand Singh, Stephen D. Brown, Terry Borer, Chris G. Sanford | 2004-08-17 |