Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for reducing dynamic power in a system

Method and apparatus for reducing dynamic power in a system

US Patent 7774729 · Granted Aug 10, 2010

Estimated economic value: $7,608,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

M/A for compiling parallel program having barrier synchronization for programmab2020
Method and apparatus for deriving signal activities for power analysis and optim2019
Metastability-hardened synchronization circuit2017
Method and apparatus for protecting, optimizing, and reporting synchronizers2016
Power-aware RAM processing2016
Method and apparatus for deriving signal activities for power analysis and optim2014
Method and apparatus for protecting, optimizing, and reporting synchronizers2014
Systems and methods for optimizing placement and routing2013
Method and apparatus for deriving signal activities for power analysis and optim2012
Power reduction techniques for components in integrated circuits2011
Method and apparatus for compiling programmable logic device configurations2011
Power-aware RAM processing2011