Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755810 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2023-09-12 |
| 10783310 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2020-09-22 |
| 10520580 | Method and system of determining an estimated position of a target electronically tagged object | Misha Nossik, Dmitry Sotnikov, Alex EFROS, Neil Teitelbaum | 2019-12-31 |
| 10140411 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2018-11-27 |
| 9536034 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2017-01-03 |
| 8935650 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2015-01-13 |
| 8898609 | Method and apparatus for integrating signal transition time modeling during routing | Ryan Fung | 2014-11-25 |
| 8739105 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2014-05-27 |
| 8533652 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2013-09-10 |
| 8296709 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2012-10-23 |
| 8095906 | Method and apparatus for performing parallel routing using a multi-threaded routing procedure | Vaughn Betz, Jordan Swartz | 2012-01-10 |
| 7441208 | Methods for designing integrated circuits | Ketan Padalia, Vaughn Betz | 2008-10-21 |
| 7412680 | Method and apparatus for performing integrated global routing and buffer insertion | Vaughn Betz, Mark Bourgeault | 2008-08-12 |
| 6915493 | Method and apparatus for providing feedback from a compactor to a router to facilitate layout of an integrated circuit | Edward G. Moulding | 2005-07-05 |