Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340220 | Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length | Quentin Éric NOUVEL, Albin Pierrick Tonnerre, Geoffray Matthieu Lacourba | 2025-06-24 |
| 12260218 | Cracking instructions into a plurality of micro-operations | Quentin Éric NOUVEL, Nicola Piano, Albin Pierrick Tonnerre, Geoffray Matthieu Lacourba | 2025-03-25 |
| 12182427 | Controlling data allocation to storage circuitry | Stefano GHIGGINI, Natalya Bondarenko, Geoffray Matthieu Lacourba, Huzefa Sanjeliwala, Miles Robert Dooley +1 more | 2024-12-31 |
| 12112169 | Register freeing latency | Geoffray Matthieu Lacourba, Cedric Denis Robert Airaud, Albin Pierrick Tonnerre | 2024-10-08 |
| 12099847 | Technique for improving efficiency of data processing operations in an apparatus that employs register renaming | Quentin Éric NOUVEL, Adrien Pesle | 2024-09-24 |
| 11972264 | Micro-operation supply rate variation | Guillaume Bolbenes, Thibaut Elie Lanois, Houdhaifa BOUZGUARROU | 2024-04-30 |
| 11847056 | Technique for controlling use of a cache to store prefetcher metadata | Damien Matthieu Valentin Cathrine, Ugo Castorina | 2023-12-19 |
| 11720494 | Cache eviction control for a private cache in an out-of-order data processing apparatus | Yohan Fernand Fargeix, Lucas Garcia, Albin Pierrick Tonnerre | 2023-08-08 |
| 11531547 | Data processing | Damian Maiorano, Cedric Denis Robert Airaud, Christophe Laurent Carbonne, Jocelyn Francois Orion Jaubert, Pasquale Ranone | 2022-12-20 |
| 11157277 | Data processing apparatus with respective banked registers for exception levels | Cedric Denis Robert Airaud, Albin Pierrick Tonnerre, Rémi Marius Teyssier | 2021-10-26 |
| 11132202 | Cache control circuitry and methods | Rémi Marius Teyssier, Cedric Denis Robert Airaud, Albin Pierrick Tonnerre, François Donati, Christophe Laurent Carbonne +1 more | 2021-09-28 |
| 11036511 | Processing of a temporary-register-using instruction including determining whether to process a register move micro-operation for transferring data from a first register file to a second register file based on whether a temporary variable is still available in the second register file | Xiaoyang Shen, Damien Robin Martin, Cedric Denis Robert Airaud, François Donati | 2021-06-15 |
| 11010159 | Bit processing involving bit-level permutation instructions or operations | Xiaoyang Shen, Cedric Denis Robert Airaud, Damien Robin Martin | 2021-05-18 |
| 10977044 | Executing branch instructions following a speculation barrier instruction | Rémi Marius Teyssier, Albin Pierrick Tonnerre, François Donati | 2021-04-13 |
| 10915327 | Apparatus and method of dispatching instructions for execution clusters based on dependencies | Rémi Marius Teyssier, François Donati, Damian Maiorano | 2021-02-09 |
| 10846098 | Execution pipeline adaptation | Cedric Denis Robert Airaud, Damien Robin Martin, Xiaoyang Shen | 2020-11-24 |
| 10725964 | Dynamic SIMD instruction issue target selection | Cedric Denis Robert Airaud, Damien Robin Martin, Xiaoyang Shen | 2020-07-28 |
| 10649782 | Apparatus and method for controlling branch prediction | Houdhaifa BOUZGUARROU, Guillaume Bolbenes | 2020-05-12 |
| 10635445 | Handling modifications to permitted program counter ranges in a data processing apparatus | Rémi Marius Teyssier, Albin Pierrick Tonnerre, Cedric Denis Robert Airaud, Guillaume Bolbenes, François Donati +2 more | 2020-04-28 |
| 10558462 | Apparatus and method for storing source operands for operations | Cedric Denis Robert Airaud, Rémi Marius Teyssier, Albin Pierrick Tonnerre | 2020-02-11 |