Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10073697 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2018-09-11 |
| 10067763 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2018-09-04 |
| 10042647 | Managing a divided load reorder queue | Richard J. Eickemeyer, Elizabeth A. McGlone, Brian W. Thompto, Albert J. Van Norstrand, Jr. | 2018-08-07 |
| 10042770 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Elizabeth A. McGlone | 2018-08-07 |
| 10037211 | Operation of a multi-slice processor with an expanded merge fetching queue | Kimberly M. Fernsler, Hung Q. Le, Elizabeth A. McGlone, Brian W. Thompto | 2018-07-31 |
| 10037229 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Sundeep Chadha, Robert A. Cordes, Hung Q. Le, Elizabeth A. McGlone | 2018-07-31 |
| 9983875 | Operation of a multi-slice processor preventing early dependent instruction wakeup | Sundeep Chadha, Elizabeth A. McGlone, Jennifer L. Molnar | 2018-05-29 |
| 9940133 | Operation of a multi-slice processor implementing simultaneous two-target loads and stores | Robert A. Cordes, Jennifer L. Molnar, Jose Angel Paredes, Brian W. Thompto | 2018-04-10 |
| 9934033 | Operation of a multi-slice processor implementing simultaneous two-target loads and stores | Robert A. Cordes, Jennifer L. Molnar, Jose Angel Paredes, Brian W. Thompto | 2018-04-03 |
| 9916245 | Accessing partial cachelines in a data cache | Richard J. Eickemeyer, Kimberly M. Fernsler, Guy L. Guthrie, Elizabeth A. McGlone | 2018-03-13 |
| 9798549 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr. +1 more | 2017-10-24 |
| 9495298 | Cache line crossing load techniques | Miles Robert Dooley | 2016-11-15 |
| 9495297 | Cache line crossing load techniques for a caching system | Miles Robert Dooley | 2016-11-15 |
| 8549235 | Method for detecting address match in a deeply pipelined processor design | Miles Robert Dooley, Scott Bruce Frommer, Sheldon B. Levenstein | 2013-10-01 |
| 8422313 | Reduced power consumption memory circuitry | Stefan Buettner, Werner Juchmes, Wolfgang Penth, Rolf Sautter | 2013-04-16 |
| 8086801 | Loading data to vector renamed register from across multiple cache lines | David Scott Ray, Bruce Joseph Ronchetti, Shih-Hsiung S. Tung | 2011-12-27 |
| 8037261 | Closed-loop system for dynamically distributing memory bandwidth | Steven B. Herndon | 2011-10-11 |
| 7809924 | System for generating effective address | Rachel Flood, Scott Bruce Frommer, Sheldon B. Levenstein, Michael Thomas Vaden | 2010-10-05 |
| 7729421 | Low latency video decoder with high-quality, variable scaling and minimal frame buffer memory | Francesco A. Campisano, Dennis P. Cheney | 2010-06-01 |
| 7360058 | System and method for generating effective address | Rachel Flood, Scott Bruce Frommer, Sheldon B. Levenstein, Michael Thomas Vaden | 2008-04-15 |
| 7318127 | Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processor | Sheldon B. Levenstein, Bruce Joseph Ronchetti, Anthony Saporito | 2008-01-08 |
| 7284094 | Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class | Sheldon B. Levenstein, Bruce Joseph Ronchetti, Anthony Saporito | 2007-10-16 |
| 7050113 | Digital video data scaler and method | Francesco A. Campisano, Bryan Lloyd | 2006-05-23 |
| 6999105 | Image scaling employing horizontal partitioning | Daniel J. Buerkle, Charles F. Marino, Chuck H. Ngai, John William Urda | 2006-02-14 |
| 6996174 | MPEG video decoder with integrated scaling and display functions | Francesco A. Campisano, Dennis P. Cheney, Chuck H. Ngai, Ronald S. Svec | 2006-02-07 |