| 9110708 |
Region-weighted accounting of multi-threaded processor core according to dispatch state |
James Wilson Bishop, Michael J. Genden, Philip L. Vitale |
2015-08-18 |
| 9015449 |
Region-weighted accounting of multi-threaded processor core according to dispatch state |
James Wilson Bishop, Michael J. Genden, Philip L. Vitale |
2015-04-21 |
| 8037261 |
Closed-loop system for dynamically distributing memory bandwidth |
David A. Hrusecky |
2011-10-11 |
| 7783957 |
Apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory |
Michael Joseph Carnevale, Daniel F. Moertl |
2010-08-24 |
| 7451380 |
Method for implementing enhanced vertical ECC storage in a dynamic random access memory |
Michael Joseph Carnevale, Daniel F. Moertl |
2008-11-11 |
| 6701397 |
Pre-arbitration request limiter for an integrated multi-master bus system |
Eric M. Foster, Eric E. Retter, Ronald S. Svec |
2004-03-02 |
| 6240492 |
Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests |
Eric M. Foster, Chuck H. Ngai |
2001-05-29 |
| 5668599 |
Memory management for an MPEG2 compliant decoder |
Dennis P. Cheney, Mark Louis Ciacelli, John D. Myers, Chuck H. Ngai |
1997-09-16 |
