Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9361268 | Splitable and scalable normalizer for vector data | Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller | 2016-06-07 |
| 9256397 | Fused multiply-adder with booth-encoding | Klaus M. Kroener, Christophe J. Layer, Silvia M. Mueller | 2016-02-09 |
| 9207995 | Mechanism to speed-up multithreaded execution by register file write port reallocation | Markus Kaltenbach, Jens Leenstra, Tim Niggemeier, Philipp Oehler, Philipp Panitz | 2015-12-08 |
| 9170771 | Residue-based error detection for a processor execution unit that supports vector operations | Juergen Haess | 2015-10-27 |
| 9164725 | Apparatus and method for calculating an SHA-2 hash function in a general purpose processor | Markus Kaltenbach, Jens Leenstra, Tim Niggemeier, Philipp Oehler, Philipp Panitz | 2015-10-20 |
| 9122517 | Fused multiply-adder with booth-encoding | Klaus M. Kroener, Christophe J. Layer, Silvia M. Mueller | 2015-09-01 |
| 8984039 | Residue-based error detection for a processor execution unit that supports vector operations | Juergen Haess | 2015-03-17 |
| 8977835 | Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency | Markus Kaltenbach, Christophe J. Layer, Jens Leenstra, Silvia M. Mueller | 2015-03-10 |
| 8949575 | Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency | Markus Kaltenbach, Christophe J. Layer, Jens Leenstra, Silvia M. Mueller | 2015-02-03 |
| 8903882 | Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product | Markus Kaltenbach, Jens Leenstra, Tim Niggemeier, Philipp Oehler, Philipp Panitz | 2014-12-02 |
| 8806253 | Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent | Tim Niggemeier, Harry Barowski, Gunnar Spiess | 2014-08-12 |
| 8626807 | Reuse of rounder for fixed conversion of log instructions | Markus Kaltenbach, Michael Klein, Silvia M. Mueller, Jochen Preiss | 2014-01-07 |
| 8578196 | Zero indication forwarding for floating point unit power reduction | Harry Barowski, Silvia M. Mueller, Tim Niggemeier, Jochen Preiss | 2013-11-05 |
| 8407275 | Fast floating point compare with slower backup for corner cases | Michael K. Kroener, Silvia M. Mueller, Jochen Preiss | 2013-03-26 |
| 8352531 | Efficient forcing of corner cases in a floating point rounder | J. Adam Butts, Silvia M. Mueller, Jochen Preiss | 2013-01-08 |
| 8346828 | System and method for storing numbers in first and second formats in a register file | Michael K. Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Claudia Schelm | 2013-01-01 |
| 8332453 | Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result | Silvia M. Mueller, Jochen Preiss, Holger Wetter | 2012-12-11 |
| 8291003 | Supporting multiple formats in a floating point processor | K. Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Claudia Schelm | 2012-10-16 |
| 8255726 | Zero indication forwarding for floating point unit power reduction | Harry Barowski, Silvia M. Mueller, Tim Niggemeier, Jochen Preiss | 2012-08-28 |
| 8245065 | Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full | Tim Niggemeier, Harry Barowski, Gunnar Spiess | 2012-08-14 |
| 8244783 | Normalizer shift prediction for log estimate instructions | Michael Klein, Jochen Preiss, Son Dao Trong | 2012-08-14 |
| 8032854 | 3-stack floorplan for floating point unit | Michael K. Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Claudia Schelm | 2011-10-04 |