Issued Patents All Time
Showing 51–75 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11068267 | High bandwidth logical register flush recovery | Steven J. Battle, Brandon Goddard, Joshua W. Bowman, Brian D. Barrick, Susan E. Eisen +2 more | 2021-07-20 |
| 11061681 | Instruction streaming using copy select vector | Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Brian W. Thompto | 2021-07-13 |
| 11030018 | On-demand multi-tiered hang buster for SMT microprocessor | Steven J. Battle, Susan E. Eisen, Kenneth L. Ward, Eula Faye Abalos Tolentino, Cliff Kucharski +2 more | 2021-06-08 |
| 10996995 | Saving and restoring a transaction memory state | Steven J. Battle, Hung Q. Le, James Wilson Bishop, Brian W. Thompto, Susan E. Eisen | 2021-05-04 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Hung Q. Le, Jessica Hui-Chun Tseng +3 more | 2021-04-20 |
| 10977034 | Instruction completion table with ready-to-complete vector | Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Deepak Singh, Gaurav Mittal +1 more | 2021-04-13 |
| 10970079 | Parallel dispatching of multi-operation instructions in a multi-slice computer processor | Kurt A. Feiste, Michael J. Genden, Paul M. Kennedy | 2021-04-06 |
| 10956158 | System and handling of register data in processors | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Thao T. Doan +2 more | 2021-03-23 |
| 10949213 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2021-03-16 |
| 10949205 | Implementation of execution compression of instructions in slice target register file mapper | Joshua W. Bowman, Hung Q. Le, Brian W. Thompto, Maureen A. Delaney, Cliff Kucharski +1 more | 2021-03-16 |
| 10942745 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Tu-An T. Nguyen, Salim A. Shah +1 more | 2021-03-09 |
| 10936321 | Instruction chaining | Kurt A. Feiste, Joshua W. Bowman, Christopher M. Mueller, Deepak Singh, Brian W. Thompto | 2021-03-02 |
| 10929144 | Speculatively releasing store data before store instruction completion in a processor | Kenneth L. Ward, Hung Q. Le, Bryan Lloyd | 2021-02-23 |
| 10909034 | Issue queue snooping for asynchronous flush and restore of distributed history buffer | David R. Terry, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Sundeep Chadha +2 more | 2021-02-02 |
| 10901743 | Speculative execution of both paths of a weakly predicted branch instruction | Kenneth L. Ward, Susan E. Eisen, Hung Q. Le | 2021-01-26 |
| 10884752 | Slice-based allocation history buffer | Brian D. Barrick, Gregory W. Alexander | 2021-01-05 |
| 10884742 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2021-01-05 |
| 10877763 | Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor | Bryan Lloyd, Brian D. Barrick, Kurt A. Feiste, Hung Q. Le, Kenneth L. Ward | 2020-12-29 |
| 10838728 | Parallel slice processor shadowing states of hardware threads across execution slices | Kurt A. Feiste, Christopher M. Mueller, Eula A. Tolentino, Tien T. Tran, Jing Zhang | 2020-11-17 |
| 10831481 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2020-11-10 |
| 10831489 | Mechanism for completing atomic instructions in a microprocessor | Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2020-11-10 |
| 10831492 | Most favored branch issue | Salma Ayub, Glenn O. Kincaid, Christopher M. Mueller, Eula Faye Abalos Tolentino, Albert J. Van Norstrand, Jr. +1 more | 2020-11-10 |
| 10831496 | Method to execute successive dependent instructions from an instruction stream in a processor | Maarten J. Boersma, Michael K. Kroener, Niels Fricke, Razvan Peter Figuli, Nandor Szirmak | 2020-11-10 |
| 10831498 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Hung Q. Le, Brian W. Thompto | 2020-11-10 |
| 10831501 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Hung Q. Le, Brian W. Thompto | 2020-11-10 |