Issued Patents All Time
Showing 76–100 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10776122 | Prioritization protocols of conditional branch instructions | Michael J. Genden, Eula Faye Abalos Tolentino, Jeffrey C. Brownscheidle, Tu-An T. Nguyen, David S. Walder | 2020-09-15 |
| 10761856 | Instruction completion table containing entries that share instruction tags | Kenneth L. Ward, Hung Q. Le, Susan E. Eisen | 2020-09-01 |
| 10747545 | Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor | Michael J. Genden, Hung Q. Le, Brian W. Thompto | 2020-08-18 |
| 10740140 | Flush-recovery bandwidth in a processor | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more | 2020-08-11 |
| 10740107 | Operation of a multi-slice processor implementing load-hit-store handling | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Kurt A. Feiste, Salim A. Shah +1 more | 2020-08-11 |
| 10725786 | Completion mechanism for a microprocessor instruction completion table | Kenneth L. Ward, Susan E. Eisen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2020-07-28 |
| 10719056 | Merging status and control data in a reservation station | Brian D. Barrick, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Michael J. Genden +2 more | 2020-07-21 |
| 10713057 | Mechanism to stop completions using stop codes in an instruction completion table | Kenneth L. Ward, Susan E. Eisen, Christopher M. Mueller, Joe Lee, Deepak Singh | 2020-07-14 |
| 10664275 | Speeding up younger store instruction execution after a sync instruction | Susan E. Eisen, Hung Q. Le, Bryan Lloyd, David Scott Ray, Benjamin W. Stolt +1 more | 2020-05-26 |
| 10649779 | Variable latency pipe for interleaving instruction tags in a microprocessor | Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski | 2020-05-12 |
| 10635444 | Shared compare lanes for dependency wake up in a pair-based issue queue | Michael J. Genden, Hung Q. Le, Brian W. Thomto | 2020-04-28 |
| 10613868 | Variable latency pipe for interleaving instruction tags in a microprocessor | Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski | 2020-04-07 |
| 10592422 | Data-less history buffer with banked restore ports in a register mapper | Brian D. Barrick, Gregory W. Alexander | 2020-03-17 |
| 10564691 | Reducing power consumption in a multi-slice computer processor | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2020-02-18 |
| 10552165 | Efficiently managing speculative finish tracking and error handling for load instructions | Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, A. James Van Norstrand, Jr., Kenneth L. Ward | 2020-02-04 |
| 10545765 | Multi-level history buffer for transaction memory in a microprocessor | Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, David R. Terry +1 more | 2020-01-28 |
| 10545762 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2020-01-28 |
| 10496412 | Parallel dispatching of multi-operation instructions in a multi-slice computer processor | Kurt A. Feiste, Michael J. Genden, Paul M. Kennedy | 2019-12-03 |
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2019-12-03 |
| 10489253 | On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor | Steven J. Battle, Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski +2 more | 2019-11-26 |
| 10445100 | Broadcasting messages between execution slices for issued instructions indicating when execution results are ready | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Dhivya Jeganathan +2 more | 2019-10-15 |
| 10423423 | Efficiently managing speculative finish tracking and error handling for load instructions | Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, A. James Van Norstrand, Jr., Kenneth L. Ward | 2019-09-24 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2019-09-10 |
| 10394565 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Hung Q. Le, Brian W. Thompto | 2019-08-27 |
| 10387147 | Managing an issue queue for fused instructions and paired instructions in a microprocessor | Michael J. Genden, Hung Q. Le, Brian W. Thompto | 2019-08-20 |