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Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor |
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Supporting speculative microprocessor instruction execution |
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On-demand multi-tiered hang buster for SMT microprocessor |
Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Kenneth L. Ward, Eula Faye Abalos Tolentino +2 more |
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Prioritization protocols of conditional branch instructions |
Michael J. Genden, Eula Faye Abalos Tolentino, Dung Q. Nguyen, Jeffrey C. Brownscheidle, Tu-An T. Nguyen |
2020-09-15 |
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Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction |
Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen +2 more |
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| 10268482 |
Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction |
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2019-04-23 |