Issued Patents All Time
Showing 101–125 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10379867 | Asynchronous flush and restore of distributed history buffer | David R. Terry, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Brian D. Barrick +2 more | 2019-08-13 |
| 10318356 | Operation of a multi-slice processor implementing a hardware level transfer of an execution thread | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Cliff Kucharski +2 more | 2019-06-11 |
| 10318294 | Operation of a multi-slice processor implementing dependency accumulation instruction sequencing | Khandker N. Adeeb, Joshua W. Bowman, Jeffrey C. Brownscheidle, Brandon Goddard, Tu-An T. Nguyen +2 more | 2019-06-11 |
| 10296337 | Preventing premature reads from a general purpose register | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2019-05-21 |
| 10296339 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le | 2019-05-21 |
| 10289415 | Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data | Susan E. Eisen, Cliff Kucharski, Hung Q. Le, David R. Terry | 2019-05-14 |
| 10282207 | Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction | Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Nasrin Sultana +2 more | 2019-05-07 |
| 10282205 | Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions | Susan E. Eisen, Cliff Kucharski, Hung Q. Le, David R. Terry | 2019-05-07 |
| 10275251 | Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file | Christopher M. Abernathy, Mary D. Brown | 2019-04-30 |
| 10268482 | Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction | Brian D. Barrick, Sundeep Chadha, Michael J. Genden, Jerry Y. Lu, Nasrin Sultana +2 more | 2019-04-23 |
| 10255071 | Method and apparatus for managing a speculative transaction in a processing unit | Salma Ayub, Susan E. Eisen, Glenn O. Kincaid, Cliff Kucharski, Christopher M. Mueller +1 more | 2019-04-09 |
| 10248426 | Direct register restore mechanism for distributed history buffers | Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Christopher M. Mueller, David R. Terry +2 more | 2019-04-02 |
| 10248421 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski +2 more | 2019-04-02 |
| 10241800 | Split-level history buffer in a computer processing unit | Hung Q. Le, David R. Terry | 2019-03-26 |
| 10241790 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski +2 more | 2019-03-26 |
| 10223196 | ECC scrubbing method in a multi-slice microprocessor | Brian D. Barrick, James Wilson Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha +2 more | 2019-03-05 |
| 10223125 | Linkable issue queue parallel execution slice processing method | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Hung Q. Le, Brian W. Thompto | 2019-03-05 |
| 10209995 | Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions | Sundeep Chadha, Richard J. Eickemeyer, John B. Griswell, Jr. | 2019-02-19 |
| 10209757 | Reducing power consumption in a multi-slice computer processor | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2019-02-19 |
| 10176038 | Partial ECC mechanism for a byte-write capable register | Dhivya Jeganathan, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2019-01-08 |
| 10175985 | Mechanism for using a reservation station as a scratch register | Sundeep Chadha, Michael J. Genden | 2019-01-08 |
| 10140127 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-11-27 |
| 10133581 | Linkable issue queue parallel execution slice for a processor | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Hung Q. Le, Brian W. Thompto | 2018-11-20 |
| 10133576 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le +1 more | 2018-11-20 |
| 10127121 | Operation of a multi-slice processor implementing adaptive failure state capture | Khandker N. Adeeb, Steven J. Battle, Brandon Goddard, Tu-An T. Nguyen, Nicholas R. Orzol +2 more | 2018-11-13 |