Issued Patents All Time
Showing 151–175 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9952874 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-04-24 |
| 9952861 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden +2 more | 2018-04-24 |
| 9940139 | Split-level history buffer in a computer processing unit | Hung Q. Le, David R. Terry | 2018-04-10 |
| 9928128 | In-pipe error scrubbing within a processor core | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Niels Fricke +1 more | 2018-03-27 |
| 9928073 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-03-27 |
| 9921833 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-03-20 |
| 9880850 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-01-30 |
| 9870039 | Reducing power consumption in a multi-slice computer processor | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2018-01-16 |
| 9870231 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2018-01-16 |
| 9870229 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2018-01-16 |
| 9870045 | Reducing power consumption in a multi-slice computer processor | Steven J. Battle, Owen Chiang, Sam Gat-Shang Chu, Saiful Islam, David R. Terry +1 more | 2018-01-16 |
| 9858078 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, David R. Terry +1 more | 2018-01-02 |
| 9851979 | Split-level history buffer in a computer processing unit | Hung Q. Le, David R. Terry | 2017-12-26 |
| 9846614 | ECC scrubbing in a multi-slice microprocessor | Brian D. Barrick, James Wilson Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha +2 more | 2017-12-19 |
| 9766975 | Partial ECC handling for a byte-write capable register | Dhivya Jeganathan, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2017-09-19 |
| 9747217 | Distributed history buffer flush and restore handling in a parallel slice design | Salma Ayub, Sundeep Chadha, Michael J. Genden, Cliff Kucharski, David R. Terry | 2017-08-29 |
| 9740620 | Distributed history buffer flush and restore handling in a parallel slice design | Salma Ayub, Sundeep Chadha, Michael J. Genden, Cliff Kucharski, David R. Terry | 2017-08-22 |
| 9720696 | Independent mapping of threads | Sam Gat-Shang Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira +1 more | 2017-08-01 |
| 9703561 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le | 2017-07-11 |
| 9639418 | Parity protection of a register | Joshua W. Bowman, Sam Gat-Shang Chu, Dhivya Jeganathan, Cliff Kucharski, David R. Terry | 2017-05-02 |
| 9531406 | Decoding of LDPC code | Evangelos S. Eleftheriou, Robert Haas, Xiao-Yu Hu | 2016-12-27 |
| 9524171 | Split-level history buffer in a computer processing unit | Hung Q. Le, David R. Terry | 2016-12-20 |
| 9489207 | Processor and method for partially flushing a dispatched instruction group including a mispredicted branch | William E. Burky, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt | 2016-11-08 |
| 9389870 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2016-07-12 |
| 9389867 | Speculative finish of instruction execution in a processor core | Sundeep Chadha, Bryan Lloyd, David Scott Ray, Benjamin W. Stolt | 2016-07-12 |