Issued Patents All Time
Showing 201–225 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7827443 | Processor instruction retry recovery | Susan E. Eisen, Hung Q. Le, Michael J. Mack, Jose Angel Paredes, Scott Barnett Swaney | 2010-11-02 |
| 7827389 | Enhanced single threaded execution in a simultaneous multithreaded microprocessor | Hung Q. Le | 2010-11-02 |
| 7809929 | Universal register rename mechanism for instructions with multiple targets in a microprocessor | Hung Q. Le, Balaram Sinharoy | 2010-10-05 |
| 7779234 | System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor | James Wilson Bishop, Hung Q. Le, Wolfram Sauer, Benjamin W. Stolt, Michael Thomas Vaden | 2010-08-17 |
| 7779233 | System and method for implementing a software-supported thread assist mechanism for a microprocessor | Hung Q. Le | 2010-08-17 |
| 7765384 | Universal register rename mechanism for targets of different instruction types in a microprocessor | Hung Q. Le, Balaram Sinharoy | 2010-07-27 |
| 7689812 | Method and system for restoring register mapper states for an out-of-order microprocessor | Christopher M. Abernathy, Mary D. Brown, Joel A. Silberman | 2010-03-30 |
| 7663963 | Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array | Sam Gat-Shang Chu, Maureen A. Delaney, Saiful Islam, Jafar Nahidi | 2010-02-16 |
| 7650486 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions | Hung Q. Le, Brian W. Thompto, Raymond Cheung Yeung | 2010-01-19 |
| 7631308 | Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors | James Wilson Bishop, Hung Q. Le, Balaram Sinharoy, Brian W. Thompto, Raymond Cheung Yeung | 2009-12-08 |
| 7620799 | Using a modified value GPR to enhance lookahead prefetch | Richard J. Eickemeyer, Hung Q. Le, Benjamin W. Stolt, Brian W. Thompto | 2009-11-17 |
| 7620801 | Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor | James Wilson Bishop, Michael Stephen Floyd, Alexander Erik Mericas, Robert Dominick Mirabella, Philip L. Vitale | 2009-11-17 |
| 7600099 | System and method for predictive early allocation of stores in a microprocessor | Hung Q. Le | 2009-10-06 |
| 7594096 | Load lookahead prefetch for microprocessors | Richard J. Eickemeyer, Hung Q. Le, Benjamin W. Stolt, Brian W. Thompto | 2009-09-22 |
| 7552318 | Branch lookahead prefetch for microprocessors | Richard J. Eickemeyer, Hung Q. Le, Benjamin W. Stolt, Brian W. Thompto | 2009-06-23 |
| 7490226 | Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor | Hung Q. Le, Raymond Cheung Yeung | 2009-02-10 |
| 7478276 | Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor | James Wilson Bishop, Hung Q. Le, Michael J. Mack, Jafar Nahidi, Jose Angel Paredes +2 more | 2009-01-13 |
| 7475226 | System for managing data dependency using bit field instruction destination vector identifying destination for execution results | Hung Q. Le | 2009-01-06 |
| 7467325 | Processor instruction retry recovery | Susan E. Eisen, Hung Q. Le, Michael J. Mack, Jose Angel Paredes, Scott Barnett Swaney | 2008-12-16 |
| 7444498 | Load lookahead prefetch for microprocessors | Richard J. Eickemeyer, Hung Q. Le, Benjamin W. Stolt, Brian W. Thompto | 2008-10-28 |
| 7421567 | Using a modified value GPR to enhance lookahead prefetch | Richard J. Eickemeyer, Hung Q. Le, Benjamin W. Stolt, Brian W. Thompto | 2008-09-02 |
| 7400548 | Method for providing multiple reads/writes using a 2read/2write register file array | Sam Gat-Shang Chu, Maureen A. Delaney, Saiful Islam, Jafar Nahidi | 2008-07-15 |
| 7395414 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions | Hung Q. Le, Brian W. Thompto, Raymond Cheung Yeung | 2008-07-01 |
| 7302553 | Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue | Sam Gat-Shang Chu, Hung Q. Le | 2007-11-27 |
| 7290261 | Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor | William E. Burky, Bjorn P. Christensen, David A. Schroter, Albert Thomas Williams | 2007-10-30 |