Issued Patents All Time
Showing 226–243 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7278011 | Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table | Susan E. Eisen, Hung Q. Le, David Arnold Luick | 2007-10-02 |
| 7254697 | Method and apparatus for dynamic modification of microprocessor instruction group at dispatch | James Wilson Bishop, Hung Q. Le, Jafar Nahidi, Brian W. Thompto | 2007-08-07 |
| 7243209 | Apparatus and method for speeding up access time of a large register file with wrap capability | Sam Gat-Shang Chu, Maureen A. Delaney, Saiful Islam, Jafar Nahidi | 2007-07-10 |
| 7243170 | Method and circuit for reading and writing an instruction buffer | Taqi Nasser Buti, Brian W. Curran, Maureen A. Delaney, Saiful Islam, Zakaria Mahmood Khwaja +1 more | 2007-07-10 |
| 7237094 | Instruction group formation and mechanism for SMT dispatch | Brian W. Curran, Brian R. Konigsburg, Hung Q. Le, David Arnold Luick | 2007-06-26 |
| 7194603 | SMT flush arbitration | William E. Burky, Hung Q. Le, David A. Schroter | 2007-03-20 |
| 7188233 | System and method for performing floating point store folding | Juergen Haess, Michael K. Kroener, Lawrence Powell, Eric M. Schwarz, Son Dao-Trong +1 more | 2007-03-06 |
| 7093106 | Register rename array with individual thread bits set upon allocation and cleared upon instruction completion | Asit S. Ambekar, Raymond Cheung Yeung | 2006-08-15 |
| 7000047 | Mechanism for effectively handling livelocks in a simultaneous multithreading processor | Raymond Cheung Yeung | 2006-02-14 |
| 6826678 | Completion monitoring in a processor having multiple execution units with various latencies | Hung Q. Le | 2004-11-30 |
| 6535973 | Method and system for speculatively issuing instructions | Hoichi Cheong, Maureen A. Delaney, Hung Q. Le, Robert G. McDonald, David Wayne Victor | 2003-03-18 |
| 6463524 | Superscalar processor and method for incrementally issuing store instructions | Maureen A. Delaney, Hung Q. Le, Robert G. McDonald, David Wayne Victor | 2002-10-08 |
| 6311267 | Just-in-time register renaming technique | Hung Q. Le | 2001-10-30 |
| 6298435 | Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor | Kin Shing Chan, Hung Q. Le | 2001-10-02 |
| 6275918 | Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold | William E. Burky, Peter Steven Lenk, David A. Schroter, Shih-Hsiung S. Tung, Michael Thomas Vaden | 2001-08-14 |
| 6134645 | Instruction completion logic distributed among execution units for improving completion efficiency | — | 2000-10-17 |
| 6128722 | Data processing system having an apparatus for exception tracking during out-of-order operation and method therefor | Richard E. Fry, Albert Thomas Williams | 2000-10-03 |
| 5465336 | Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system | Benjamin Imai, Hung Q. Le | 1995-11-07 |