DN

Dung Q. Nguyen

IBM: 242 patents #113 of 70,183Top 1%
Globalfoundries: 1 patents #2,221 of 4,424Top 55%
🗺 Texas: #50 of 125,132 inventorsTop 1%
Overall (All Time): #2,136 of 4,157,543Top 1%
243
Patents All Time

Issued Patents All Time

Showing 176–200 of 243 patents

Patent #TitleCo-InventorsDate
9384002 Speculative finish of instruction execution in a processor core Sundeep Chadha, Bryan Lloyd, David Scott Ray, Benjamin W. Stolt 2016-07-05
9367322 Age based fast instruction issue Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney 2016-06-14
9286068 Efficient usage of a multi-level register file utilizing a register file bypass Christopher M. Abernathy, Mary D. Brown, Sundeep Chadha 2016-03-15
8874880 Instruction tracking system for processors Christopher M. Abernathy, Hung Q. Le, Benjamin W. Stolt 2014-10-28
8725993 Thread transition management Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James Allan Kahle, Hung Q. Le 2014-05-13
8661228 Multi-level register file supporting multiple threads Christopher M. Abernathy, Mary D. Brown, Hung Q. Le 2014-02-25
8661227 Multi-level register file supporting multiple threads Christopher M. Abernathy, Mary D. Brown, Hung Q. Le 2014-02-25
8631223 Register file supporting transactional processing Christopher M. Abernathy, Mary D. Brown, Hung Q. Le 2014-01-14
8521998 Instruction tracking system for processors Christopher M. Abernathy, Hung Q. Le, Benjamin W. Stolt 2013-08-27
8489863 Processor including age tracking of issue queue instructions James Wilson Bishop, Mary D. Brown, Jeffrey C. Brownscheidle, Robert A. Cordes, Maureen A. Delaney +2 more 2013-07-16
8418180 Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors James Wilson Bishop, Hung Q. Le, Balaram Sinharoy, Brian W. Thompto, Raymond Cheung Yeung 2013-04-09
8417925 Processor register recovery after flush operation 2013-04-09
8386753 Completion arbitration for more than two threads based on resource limitations Susan E. Eisen, Balaram Sinharoy, Benjamin W. Stolt 2013-02-26
8380964 Processor including age tracking of issue queue instructions James Wilson Bishop, Mary D. Brown, Jeffrey C. Brownscheidle, Robert A. Cordes, Maureen A. Delaney +2 more 2013-02-19
8347068 Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor Richard J. Eickemeyer, Hung Q. Le, Balaram Sinharoy 2013-01-01
8271765 Managing instructions for more efficient load/store unit usage Pradip Bose, Alper Buyuktosunoglu, Michael Stephen Floyd, Bruce Joseph Ronchetti 2012-09-18
8245018 Processor register recovery after flush operation 2012-08-14
8145887 Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor Hung Q. Le 2012-03-27
8108655 Selecting fixed-point instructions to issue on load-store unit Christopher M. Abernathy, James Wilson Bishop, Mary D. Brown, William E. Burky, Robert A. Cordes +2 more 2012-01-31
8086826 Dependency tracking for enabling successive processor instructions to issue Mary D. Brown, William E. Burky, Balaram Sinharoy 2011-12-27
8046566 Method to reduce power consumption of a register file with multi SMT support Christopher M. Abernathy, Jens Leenstra, Nicolas Maeding 2011-10-25
8041928 Information handling system with real and virtual load/store instruction issue queue William E. Burky, Kurt A. Feiste, Balaram Sinharoy, Albert Thomas Williams 2011-10-18
8037366 Issuing instructions in-order in an out-of-order processor using false dependencies Christopher M. Abernathy, Mary D. Brown, Todd A. Venton 2011-10-11
7979677 Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor 2011-07-12
7877580 Branch lookahead prefetch for microprocessors Richard J. Eickemeyer, Hung Q. Le, Benjamin W. Stolt, Brian W. Thompto 2011-01-25